Digital power control and management and PMBus programming

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Digital power control and management and PMBus programming [Copy link]

Digital power is divided into two parts: digital power control and digital power management. "Digital power control" refers to the use of digital feedback loops to regulate voltage and current. "Digital power management" means that power supply output characteristics such as voltage and current limits can be configured through a serial link. It also means that real-time voltage, current and operating temperature measurements can be sent to an external system controller through the same link.

This article focuses on pulse width modulation (PWM), pulse density modulation (PDM), and pulse frequency modulation (PFM) switching regulators and controller ICs. Some of these integrate the driver that controls the transistor or transistors that actually switch, others do not. Still others even integrate the switching FETs if they provide the right load. So the question of digital versus analog depends on how the regulator's control loop is closed.

Figure 1 shows variations on the two most common PWM switch topologies, the step-down and step-up (buck/boost) converters. In a synchronous configuration, a second transistor replaces the diode. The use of pulse-width modulation makes these converters "quasi-digital" in a sense, at least compared to a 723-type linear regulator based on a series pass element. In fact, PWM makes it possible to use a digital control loop. However, the converters in Figure 1 lack circuitry to control the duty cycle of one or more switches, which can be implemented in the analog or digital domain.

Regardless of whether analog or digital techniques are used, there are two ways to implement a feedback loop: voltage mode and current mode. For simplicity, let’s first consider how it is implemented in the analog domain.

Figure 1: A switch-mode DC-DC power supply without a controller is quite simple. Whether used to step up or step down a voltage, its success depends on how the designer arranges some basic components.

In a voltage-mode topology, a sample of the output voltage is subtracted from a reference voltage to create a small error signal that is compared to the oscillator ramp signal (Figure 2). As the circuit output voltage changes, the error voltage also changes, which in turn changes the comparator threshold. This, in turn, causes the output signal width to change. These pulses control the on-time of the regulator's switching transistor. As the output voltage increases, the pulse width becomes smaller.

One advantage of current-mode control is its ability to manage inductor current. A regulator using current-mode control has a current loop nested within a slower voltage loop. This inner loop senses the peak current of the switching transistor and keeps the current constant by controlling the on-time of each transistor on a pulse-by-pulse basis.

Figure 2: Voltage-mode feedback (in this case in the analog domain) comprises a control loop.

At the same time, the outer loop senses the DC output voltage and provides a control voltage to the inner loop. In this circuit, the slope of the inductor current generates a ramp that is compared to the error signal. When the output voltage drops, the controller provides more current to the load (Figure 3).

In these control topologies, the gain of the control loop cannot exceed unity at any frequency where the phase shift of the loop reaches 360°. The phase shift includes the inherent 180° phase shift caused by feeding the control signal into the inverting input of the feedback op amp, the additional delays of the amplifier and other active components, and the delays introduced by capacitors and inductors (especially the large capacitors of the output filter).

Stabilizing the loop requires compensation for gain variations and phase shifts over a range of frequencies. Traditionally, stabilizing a power supply with analog PWM has usually required an empirical approach: you experiment with different combinations of passive components on an actual board laid out identically to the production board, and observe the circuit's time-domain response as the supply voltage and load demands are varied. Lately, things have gotten much easier, as analog controller companies now implement various "insert a value in a register" features first introduced on digital controllers in their own models.

Figure 3: Current mode feedback uses a nested feedback loop. Unlike voltage mode, it needs to account for the current in the inductor.

Digital control loop

Most digital implementations of voltage-mode control consist of an analog-to-digital converter (ADC), a microcontroller or DSP that implements some control algorithm, and a digital pulse-width modulator (DPWM) that picks up the controller output and produces the signal needed to drive one or more transistors that perform the switching action (Figure 4).

First, the ADC generates a digital representation of the output voltage that is fed into the controller. The control algorithm is the familiar proportional-integral (PI) or proportional-integral/differential (PID) algorithm.

In a PID controller (a more complex example), each ADC input is subject to an algorithm based on a series of coefficients. The proportional coefficient is a gain factor that is related to sensitivity. The integer coefficient adjusts the PWM duty cycle according to how long the error occurs. The induction coefficient compensates for the time delay of the loop (phase is more effective). Combined, the coefficients of the PID algorithm determine the frequency response of the system.

The controller then converts the ADC's output voltage representation into the pulse duration (duty cycle) information required to maintain the desired output voltage. This information is then passed to a DPWM, which performs the same drive signal generation function as the analog PWM.

Note the difference between the analog and digital control schemes in managing the switching transistor. The analog controller triggers the switching transistor to the ON state at the rising edge of the clock and triggers the transistor to the OFF state when the voltage ramp reaches a preset threshold voltage; the PID controller calculates the required duration of the ON and OFF states of the switching transistor.

In theory, analog control can provide a continuous precision output voltage, but the interaction of ADC precision and sampling rate, coupled with the DPWM switching rate, makes the situation somewhat complicated.

For example, the DPWM must have a higher accuracy than the ADC. Otherwise, a 1LSB change in the ADC output may cause the DPWM to change the output voltage by more than 1LSB. As a result, the output voltage switches steadily between two values, a state known as "limited looping."

Figure 4: The digital implementation of voltage-mode control eliminates the sawtooth generator. In other respects, they correspond closely to the analog implementation.

Avoiding loops is not easy, however. This is because providing the DPWM with higher precision means increasing its pulse rate (which determines how many bits can be generated in any given period of time). However, the DPWM pulse rate limits the time it has to compress all the bits coming from the controller. If a DPWM has a 1MHz switching rate and a 10-bit ADC, then calculations show that the modulator requires a pulse rate of more than 1 GHz.

Of course, such high speeds are impractical, so the designer of the digital controller must find an alternative solution. One solution is to introduce some DPWM clock jitter. The regulator output filter averages any pulse train fed into it, which makes it possible to adjust the width of each mth output pulse by the equivalent of 1 LSB.

This increases or decreases the average value of the pulse train by a factor of 1/m with 1 LSB accuracy. If 1 LSB at the controller input changes the output pulse train by an average of 10 mV, this will shorten every four pulses by 10 mV, and the average output voltage through the filter will be reduced by 10 mV/4, or 2.5 mV.

When a system has more than one voltage rail, it becomes important to turn on the voltage rails in the correct sequence and control the rate of change of the voltage when the power is turned on and off. In systems with multiple power rails, digital power management makes it easier to program the order and timing of the different voltage rails.

It is not necessary for a power converter or controller to have both digital power control and digital power management. Today, some DC/DC regulators use analog control but offer enhanced programmability on the I ² C bus; others use digital feedback but can set operating characteristics by connecting specific pins directly to ground or through resistors to ground. Today, much of the power management and some of the power control functions are implemented through the Power Management Bus (PMBus).

Figure 5: Basic PMBus requires only the clock and data lines; the ALERT#, CONTROL, and WriteProtect lines are optional.

PMBus Interface and Programming

The data sheets for most power management and control ICs define the communication interface as I ² C. But upon closer inspection, you'll find that the real interface is the System Management Bus (SMBus), and the communication protocol is often PMBus.

PMBus is an open standard owned by the System Management Interface Forum (Figure 5). In addition to using the SMBus transport layer, the specification adds a control language for power supply design. PMBus is the result of collaboration between power supply companies and semiconductor companies.

PMBus uses SMBus version 1.1 as its base specification. However, version 1.1 is not the current version of SMBus. The main difference between version 1.1 and the current version 2.0 is the address bus arbitration feature, which is not necessary for power products because the address of each power supply almost always gives its physical address and system function.

The first part of the PMBus specification defines the general requirements, transmission and electrical interface and physical layer, while the second part defines the data command language and its format between the power business controller or system master and the power device.

In the PMBus specification, PMBus ICs, power converters, power supplies, etc. are all referred to as "devices." However, a single device is not necessarily required to support all features, functions, and commands. However, to comply with the PMBus specification, a device must: 1) meet all requirements in Part I; 2) support at least one non-manufacturer-specific command in Part II; 3) correctly perform the functions defined by the PMBus command code; 4) accept, recognize and execute PMBus commands, or reject them; 5) start and operate safely without communicating with other PMBus devices when the power supply is powered on; 6) use SMBus for transmission (with exceptions); 7) support the Group Command Protocol for sending commands to multiple PMBus devices (these commands are received in one transmission, and when the devices detect the STOP condition that terminates the command, they begin to execute the received command); 8) respond when the hardware line signal state changes (there is no requirement for response time); 9) provide output voltage accuracy and other parameters that can be set and reported in the product documentation.

The PMBus specification also provides some functions that manufacturers may implement if they need to, including: supporting the SMBus PEC protocol; temporarily acting as a bus master and communicating with the master; notifying the master that they want to communicate with the master; write protect (WP) signal input; and firmware upgrades through the SMBus interface.

The PMBus specification defines two required signals and three optional signals (Figure 6): the required signals are the clock signal (SCL) and the data signal (SDA), and the optional signals are SMBALERT#, CONTROL, and WP. SCL, SDA, and SMBALERT# are valid when they are pulled down to a low voltage, and the voltage of CONTROL and WP is the same as the logic voltage of PMBus in most cases.

SMBALERT# is a line or signal that is initiated by any slave that needs to be supported by the PMBus master. When SMBALERT# is active, the master sends the alert response address on the PMBus, and then each alerting device puts its device address on SDA. There is an arbitration mechanism to manage conflicts.

Once a device has successfully placed its address on the bus, it releases the SMBALERT# line. Although the PMBus specification labels this signal as "optional," its use is recommended and some OEMs require it in their devices.

Some system OEMs also require a CONTROL signal. CONTROL provides a quick way to turn off the PMBus-enabled power output. OEMs rarely require the WP signal, which is used to protect data and program information from accidental modification.

The PMBus data packet protocol is identical to the SMBus protocol, except that it includes an extension called the Group-Command Protocol that allows multiple devices to be synchronized using the STOP bit detection.

In a group command protocol, a PEC byte may be added to the end of each command and data packet, followed by repeated START bits and the address, command, and data sent to the next device until all devices are configured. At the end of the configuration packet for the last device, the STOP bit is sent. When the STOP bit is detected, all devices act according to the command sent (or, in other words, synchronize multiple devices using the CONTROL line).

Figure 6: In an implementation of the PMBus specification, the SMBus provides serial communications between a host computer or system manager and PMBus-compliant devices.

PMBus Command Language

The PMBus command language provides more than 100 basic command codes and codes reserved for specific manufacturer and user commands, and also supports future extensions of the basic commands. However, most PMBus devices cannot implement all PMBus commands.

Because a device only has to support one core command to comply with the PMBus specification, there are some specifications for notifying the PMBus master that a command is not supported, including responding to the command code or subsequent data bytes with a negative acknowledgement (NACK), or responding to the command and data with an ACK, but then alerting the master that there is a problem. This allows the master to read the command STATUS_BYTE to determine the problem. Compared with NACK, it reduces uncertainty because NACK can mean "I didn't hear you", "I can't support you", or "I don't understand you".

The PMBus specification allows engineering values to be encoded in at least two formats: text and direct. The text format exchanges data in engineering units such as volts, amps, microseconds, or degrees Celsius. The direct format is based on the slave's internal units, which reduces the computational power required of the slave, but at the expense of complexity on the master, which must have the information to translate the master's units into the slave's units. The text format requires the least amount of work on the master, but it requires the slave to convert the internal values into engineering units.

In addition to the text and direct formats, output voltages can be expressed in a simpler format called VID. Although VID regulation cannot meet the timing requirements of dynamic processor power supplies (because the bus bandwidth is too low), VID provides a simple way to manage voltage outputs. In addition, it does not require high complexity in the master and slaves.

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