【Information】NVMe host controller, AMBA-AXI4 interface, Xilinx FPGA, introduction and user manual

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【Information】NVMe host controller, AMBA-AXI4 interface, Xilinx FPGA, introduction and user manual [Copy link]

NVMe AXI4 Host Controller IP

introduce

NVMe AXI4 Host Controller IP can connect to high-speed storage PCIe SSD without CPU, automatically accelerate the processing of all NVMe protocol commands, and has independent data writing and reading AXI4 interfaces. It is suitable not only for high-performance, sequential access applications, but also for random access applications. At the same time, combined with external memory (such as DDR), it makes data access management on the Host side more flexible.

Without the need for a CPU, the NVMe AXI4 Host Controller IP automatically performs PCIe device enumeration and configuration, NVMe controller identification and initialization, NVMe queue setting and initialization for PCIe SSDs, and implements the required and optional NVMe Admin Command Set and NVM Command Set, as well as PCIe SSD reset/power-off/SMART/Error Information/Device Self-test management, IO (Page) read/write, DMA read/write, and data erase functions, providing users with a simple and efficient interface to achieve high-performance storage solutions.

The sequential transfer length of the NVMe AXI4 Host Controller IP read and write is dynamically configurable during RTL runtime, with a minimum of 4K-Byte and a maximum of 512K-Byte. For each read and write access, the user can specify the sequential transfer length (4K~512K Byte) of this transfer. Different sequential transfer lengths correspond to different DMA read and write performance.

For multiple data channels accessing PCIe SSD, NVMe's multi-queue feature is used. NVMe AXI4 Host Controller IP supports flexible configuration of the number of DMA read and write channels. According to the NVMe queue priority arbitration (round-robin arbitration or weighted round-robin arbitration) mechanism, multiple DMA channels can efficiently access the same PCIe SSD, thereby meeting the parallel requirements and QoS requirements of multiple data channel access.

1. characteristic
Support Ultrascale+, Ultrascale, 7 Series FPGA
Support PCIe Gen4, PCIe Gen3, PCIe Gen2 SSD
No CPU required
Automatically implement PCIe device enumeration, NVMe controller identification, and NVMe queue settings for PCIe SSDs
Support NVM Subsystem Reset, Controller Reset and Shutdown for PCIe SSD
Support NVMe Admin Command Set: Identify, SMART, Error Information, Device Self-test, Create/Delete IO Submission/Completion Queue, Set Features – Volatile Write Cache/Arbitration
Support NVMe NVM Command Set: Write, Read, Flush, Dataset Management
Provides an Admin command interface to implement PCIe SSD reset/power off/SMART/Error Information/Device Self-test management functions
Provides 1 IO command interface to implement IO (Page) read and write, Cache Flush and logical data block erase functions for PCIe SSD; provides 1 IO-AXI4-MM interface to read and write IO (page) data
Provides a DMA command interface to implement DMA read and write functions for PCIe SSD
1. Provides a DMA-AXI4 interface to implement DMA data input and output
The sequential transfer length of DMA read and write can be dynamically configured, 4K-Byte~512K-Byte; different sequential transfer lengths correspond to different DMA read and write performance
For multi-channel DMA requirements, 4 DMA command interfaces and 1 DMA-AXI4 interface can be configured
The number of NVMe queues (number of configured DMA channels) and depth are configurable to balance the DMA performance of PCIe SSD and the consumed logic resources.
Supports Round Robin Arbitration and Weighted Round Robin Arbitration
Supports timeout and error handling recovery mechanisms for NVMe Admin and IO commands, and provides detailed and extended access error status output
Supported NVMe devices:
1. Base Class Code: 01h (mass storage), Sub Class Code: 08h (Non-volatile), Programming Interface: 02h (NVMHCI)
2. MPSMIN (Memory Page Size Minimum): 0 (4K-byte)
3. MDTS (Maximum Data Transfer Size): greater than or equal to the sequential transfer length or 0 (unlimited)
4. LBA Unit: 512-byte, 1024-byte, 2048-byte or 4096-byte
An NVMe AXI4 Host Controller IP directly connected to the PCIe SSD
Synchronous, synthesizable Verilog design for easy integration
Fully validated NVMe AXI4 Host Controller IP

1. performance

PCIe configuration parameters: Max Payload Size = 256-byte, Max Read Request Size = 512-byte

PCIe Gen3 SSD (Samsung 990 Pro 4TB), Seq=512KB, 1 DMA channel:
1. DMA write speed 3380MB/s
2. DMA read speed 3550MB/s
PCIe Gen3 SSD (Samsung 970EVO Plus 1TB), Seq=512KB, 1 DMA channel:
1. DMA write speed 3320MB/s
2. DMA read speed 3480MB/s
PCIe Gen3 SSD (Intel D5-P5530 3.84TB), Seq=512KB, 1 DMA channel:
1. DMA write speed 3350MB/s
2. DMA read speed 3440MB/s
PCIe Gen3 SSD (Samsung 980 Pro 1TB), Seq=512KB, 1 DMA channel:
1. DMA write speed 2950MB/s
2. DMA read speed 3430MB/s

NVMe AXI4 Host Controller User Guide.pdf (795.17 KB, downloads: 0)

NVMe AXI4 Host Controller IP.pdf (236.03 KB, downloads: 0)

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NVMe AXI4 Host Controller User Guide.pdf (795.17 KB, downloads: 0)

NVMe AXI4 Host Controller IP.pdf (236.03 KB, downloads: 0)