The Hitchhiker's Guide to Chip Authentication

arui1999

The Hitchhiker's Guide to Chip Authentication [Copy link]

 

In this book, Liu Bin (Lu Sang), a senior verification expert, will give you a comprehensive introduction to the theory and practice of verification, and provide an integrated solution for dynamic verification for system design. This is a chip verification textbook for college students majoring in integrated circuit design. It is a model of industry-university integration in the IC industry and has been put into teaching at the Demonstration Microelectronics College and has been tested.

Chapter 1 Chip Verification in Full View

1.1 Introduction to Functional Verification

1.2 The Situation of Verification

1.3 Five Dimensions of Verification Capability

1.4 Verification tasks and objectives

1.5 Verification cycle

1.6 Chapter Conclusion

Chapter 2 Verification Strategy

2.1 Design Process

2.2 Levels of Verification

2.3 Transparency of verification

2.4 Principles of motivation

2.5 Inspection methods

2.6 Integrated Environment

2.7 Chapter Conclusion

Chapter 3 Verification Methods

3.1 Dynamic Simulation

3.2 Static Check

3.3 Development Environment

3.4 Virtual Model

3.5 Hardware Acceleration

3.6 Performance Verification

3.7 Performance Verification

3.8 Trend Outlook

3.9 Chapter Conclusion

Chapter 4 Validation Plan

4.1 Program Overview

4.2 Contents of the Plan

4.3 Implementation of the plan

4.4 Planned Progress Evaluation

4.5 Chapter Conclusion

Chapter 5 Verification Management

5.1 Verification Cycle Checklist

5.2 Three Elements of Verification Management

5.3 Convergence of verification

5.4 Make loopholes have nowhere to hide

5.5 Team Building

5.6 Training of Verifiers

5.7 Specialization of Verification

5.8 Chapter Conclusion

Chapter 6: Verification Structure

6.1 Test Platform Overview

6.2 Hardware Design Description

6.3 Excitation Generator

6.4 Monitor

6.5 Comparator

6.6 Verification Structure

6.7 Chapter Conclusion

Chapter 7 SV Environment Construction

7.1 Data Types

7.2 Module Definition and Instantiation

7.3 Interface

7.4 Programs and modules

7.5 Testing from beginning to end

7.6 Chapter Conclusion

Chapter 8 SV Component Implementation

8.1 Driving the Excitation Generator

8.2 Encapsulation of the Excitation Generator

8.3 Randomization of the stimulus generator

8.4 Monitor sampling

8.5 Communication between components

8.6 Comparator and Reference Model

8.7 Reporting Specifications for the Test Environment

8.8 Chapter Conclusion

Chapter 9 SV System Integration

9.1 The meaning of packages

9.2 Verification Environment Assembly

9.3 Test scenario generation

9.4 Flexible Configuration

9.5 A Preliminary Discussion on Environment Reusability

9.6 Chapter Conclusion

Chapter 10 UVM Worldview

10.1 The Verification Era We Are In

10.2 Class Library Map

10.3 Factory Mechanism

10.4 Core Base Classes

10.5 Phase Mechanism

10.6 Config Mechanism

10.7 Message Management

10.8 The pros and cons of macros

10.9 Chapter Conclusion

Chapter 11 UVM Structure

11.1 Component Family

11.2 How to install DUT into TB?

11.3 The inner canon of building environment

11.4 Chapter Conclusion

Chapter 12 UVM Communication

12.1 Introduction to TLM Communication

12.2 One-way, two-way and multi-way communication

12.3 Communication Pipeline Application

12.4 TLM2 Communication

12.5 Synchronous Communication Elements

12.6 Chapter Conclusion

Chapter 13 UVM Sequence

13.1 Getting Started

13.2 Sequence and Item

13.3 Sequencer and Driver

13.4 Sequencer and Sequence

13.5 Sequence Hierarchy

13.6 Chapter Conclusion

Chapter 14 UVM Registers

14.1 Register Model Overview

14.2 Integration of Register Model

14.3 General approach to register models

14.4 Scenario Application of Register Model

14.5 Chapter Conclusion

Chapter 15 Verification Platform Automation

15.1 Why do we need a code generator?

15.2 UVM Framework

15.3 How to customize a TB automation tool

15.4 Chapter Conclusion

Chapter 16 Cross-platform porting and reuse

16.1 Portable Stimulus Standard (PSS)

16.2 Overview of PSS Toolset

16.3 Cross-platform verification structure considerations

16.4 Chapter Conclusion

Chapter 17 SV and UVM Interface Application

17.1 DPI Interface and C Test

17.2 SystemC and UVM TLM2 Communication

17.3 Hybrid Simulation of MATLAB and Simulink Models with UVM

17.4 Interaction between scripting languages and UVM

17.5 Chapter Conclusion

Chapter 18 SV and UVM Advanced Topics

18.1 SystemVerilog Open Source Public Library

18.2 SVUnit

18.3 OVM to UVM Migration

18.4 Hybrid Simulation of OVM and UVM

18.5 Chapter Conclusion

references

https://download.eeworld.com.cn/detail/sigma/622651