[Domestic high-performance motion control MCU Xianji HPM5361] PLB Overview-How to configure in/out signals to chip pins?

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[Domestic high-performance motion control MCU Xianji HPM5361] PLB Overview-How to configure in/out signals to chip pins? [Copy link]

 

Function

1 Programmable Logic Unit (PLB). PLB supports combinational logic operations and counting operations.

The various signals of PLB can be flexibly allocated through the interconnection manager in the motor control unit and can be connected to various IOs of TRGM (how to configure???).

It can also connect to other on-chip peripherals.

● Trigger input from the interconnection manager in the motor control unit

● Trigger output, connected to the interconnection manager in the motor control unit

Interconnect Manager

The input and output of the PLB are configured by the interconnect manager, Section 32.8

Interconnection Manager Input P414

Interconnect output P418

Output Configuration

Related registers TRGOCFG[PLB_IN_xx] P453

This register selects which input of TRGM the corresponding interconnect manager output signal PLB_IN_xx comes from.

And set the output filtering polarity control, etc.

For example, TRGOCFG[PLB_IN_00] configures the input of the interconnect output signal PLB_IN_00.

The register description is as follows P457

PLB Structure

PLB consists of two structures

● TYPE_A can realize combinational logic + sequential logic programming

● TYPE_B can realize complex operations such as counting, displacement, filtering, etc.

The input and output of PLB are connected in TRIG_MUX.

32 input and output signals, corresponding to the previous PLB_IN_00~PLB_IN_31, PLB_OUT_00~PLB_OUT_31

A type structure is as follows

The structure of type B is as follows

There are 4 TYPE A channels, each with 4 trig_in inputs and 4 trig_out outputs. Each trig_out output corresponds to a lookup table unit. The 4 lookup tables all use 4-bit trig_in as an index, and the content of the lookup table can be regarded as a truth table of 4-bit trig_in. The 4 lookup tables use the same trig_in, and the trig_in of different TYPE A modules increases in sequence, for example, TYPE A 0 uses trig_in[3:0], and TYPE A 1 uses trig_in[7:4].

The output of the lookup table is output to trig_out using a register.

Software can configure TYPE_A[SW_INJECT] to inject directly into trig_out. The injected value will be maintained for one system clock cycle, after which the value of trig_out will continue to be determined by trig_in and the lookup table.

Type B is more complicated and will be discussed later.

PLB Register

Type A related registers are as follows, and the four channels are similar.

Each channel has 4 lookup tables, that is, LOOKUP_TABLE is 0~3,

So there are actually only two registers: the lookup table register and the SW_INJECT register

Lookup table 16-bit value is the truth table of 4-bit input.

There are 16 cases for 4-bit input, one case corresponds to one bit.

for example

input Output

0 0 0 0 1

Then bit0=1

For example, input

input Output

0 0 0 1 0

Then bit1=0

The x in Bitx is the binary code corresponding to the 4-bit input, and the corresponding bit is the corresponding output.

Software injection, that is, forcing the trig out to output a certain state for one cycle.

4 bits correspond to 4 trig out outputs, and one bit corresponds to one trig out signal, for a total of 4 signals.

This signal is maintained for only one clock cycle.

question

It seems that interconnect management is all internal signals? Can the input and output of PLB be mapped to specific IO?

How to map trig_inx and trig_outx in the figure below to a specific pin of the chip?

The manual is not clearly described. I read it several times but still couldn't understand it. The manual is not very detailed.