[Analysis Notes] Analysis of the problem that the Allwinner T507 PF4 pin cannot be set to interrupt mode normally

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[Analysis Notes] Analysis of the problem that the Allwinner T507 PF4 pin cannot be set to interrupt mode normally [Copy link]

 

## Related information Hardware platform: Allwinner T507 System version: Android 10 / Linux 4.9.170 Problem description: PF4 cannot be set to interrupt mode through the standard interface, while PF1, PF2, PF3, and PF5 are available. ## At the beginning of the analysis process, it was thought that the pin was occupied by other drivers, or the pin did not have an interrupt function. After investigation, these two possibilities have been ruled out, so the root cause of the problem was found by analyzing the source code. The following is an analysis using the gpio_keys.c driver as the entry point: ```c // drivers/input/keyboard/gpio_keys.c static int gpio_keys_setup_key(struct platform_device *pdev, struct input_dev *input, struct gpio_button_data *bdata, const struct gpio_keys_button *button) { ...... error = devm_request_any_context_irq( &pdev->dev, bdata->irq, isr, irqflags, desc, bdata); } // kernel/irq/devres.c int devm_request_any_context_irq(struct device *dev, unsigned int irq, irq_handler_t handler, unsigned long irqflags, const char *devname, void *dev_id) { ...... rc = request_any_context_irq (irq, handler, irqflags, devname, dev_id); if (rc < 0) { devres_free(dr); return rc; } ...... return rc; } // kernel/irq/manage.c int request_any_context_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev_id) { ...... ret = request_irq(irq , handler, flags, name, dev_id); return !ret ? IRQC_IS_HARDIRQ : ret; } // include/linux/interrupt.h static inline int __must_check request_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev) { return request_threaded_irq(irq, handler, NULL, flag s, name, dev); } // kernel/irq/manage.c int request_threaded_irq(unsigned int irq, irq_handler_t handler, irq_handler_t thread_fn, unsigned long irqflags, const char *devname, void *dev_id) { ...... chip_bus_lock(desc); retval = __setup_irq(irq, desc, action); chip_bus_sync_unlock(desc) c); ...... return retval; } // kernel/irq/manage.c static int __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) { ...... if (!shared) { ret = irq_request_resources(desc); if (ret) { pr_err("Failed to request resources for %s (irq %d) on irq chip %s\n", new->name, irq, desc->irq_data.chip->name); goto out_mask; } ...... } ...... } // kernel/irq/manage.c static int irq_request_resources(struct irq_desc *desc) { struct irq_data *d = &desc->irq_data; struct irq_chip *c = d->chip; return c->irq_ request_resources ? c->irq_request_resources(d) : 0; } // drivers/pinctrl/sunxi/pinctrl-sunxi.c static struct irq_chip sunxi_pinctrl_edge_irq_chip = { .name = "sunxi_pio_edge", .irq_ack = sunxi_pinctrl_irq_ack, .irq_mask = sunxi_pinctrl_ir q_mask, .irq_unmask = sunxi_pinctrl_irq_unmask, .irq_request_resources = sunxi_pinctrl_irq_request_resources, .irq_release_resources = sunxi_pinctrl_irq_release_resources, .irq_set_type = sunxi_pinctrl_irq_set_type, .irq_set_wake = sunxi_pinctrl_irq_set _wake, }; // drivers/pinctrl/sunxi/pinctrl-sunxi.c static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); struct sunxi_desc_function *func; func = sunxi_pinctrl_desc_find_function_by_pin(pctl, pctl->irq_array[d->hwirq], "ir q"); if ( !func) return -EINVAL; /* Change muxing to INT mode */ printk(KERN_EMERG"[lmx] irq:%d set int mode pin:%d d->hwirq:%ld func->muxval:%d\n ", d->irq, pctl->irq_array[d->hwirq], d->hwirq, func->muxval); sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); return 0; } // drivers/pinctrl/sunxi/pinctrl-sunxi.c static void sunxi_pmx_set(struct pinctrl_dev *pctldev, unsigned pin, u8 config) { struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; u32 val, mask; raw_spin_lock_irqsave(&pctl->lock, flags); pin -= pctl->desc->pin_base; val = readl (pctl->membase + sunxi_mux_reg(pin)); mask = MUX_PINS_MASK << sunxi_mux_offset(pin); writel((val & ~mask) | config << sunxi_mux_offset(pin), pctl->membase + sunxi_mux_reg(pin)); raw_spin_unlock_irqrestore(&pctl->lock, flags); } ``` No matter how complicated the code is, it is ultimately necessary to control the chip by reading and writing registers Through the above code analysis, we can find that the sunxi_pmx_set() interface is used to configure registers. It is the lowest level interface. We can check whether there is any problem by printing out the passed parameters. PF3 prints: ```bash [ 10.683205] [lmx] irq:148 set int mode pin:163 d->hwirq:131 func->muxval:6 ``` PF4 prints: ```bash [ 10.683557 ] [lmx] irq:149 set int mode pin:196 d->hwirq:132 func->muxval:6 ``` Here we can see something very strange, the pin number of PF3 is 163, while that of PF4 is 196, that’s a huge span. You can query the correct pin number of PF4 through the following command, and also know which group the 196 pin number belongs to: ```bash mercury-demo:/ # cat /sys/kernel/debug/pinctrl/pio/pins registered pins: 137 ...... pin 160 (PF0) pin 161 (PF1) pin 162 (PF2) pin 163 (PF3) pin 164 (PF4) pin 165 (PF5) pin 166 (PF6) ...... pin 196 (PG4) pin 197 (PG5) ...... ``` Confirm that the correct pin number of PF4 is 164, and 196 corresponds to PG4. The actual effective one is PG4. You can confirm it by running the following command: ```bash mercury -demo:/sys/kernel/debug/sunxi_pinctrl # echo PG4 > sunxi_pin mercury-demo:/sys/kernel/debug/sunxi_pinctrl # cat * pin[PG4] data: 1 pio pin[PG4] dlevel: 1 pin[PG4] function: 6 NOMATCH pin[PG4] pull: 1 PG4 pin[PG4] funciton: 6 pin[PG4] data: 1 pin[PG4] dlevel: 1 pin[PG4] pull: 1 ``` According to the code, the pin number comes from the pctl->irq_array array, and is assigned by pctl->irq_array. Print out whether there is an error at the beginning: ```c // drivers/pinctrl/sunxi/pinctrl-sunxi.c static int sunxi_pinctrl_build_state(struct platform_device *pdev) { ...... /* Count functions associated groups * / for (i = 0; i < pctl->desc->npins; i++) { const struct sunxi_desc_pin *pin = pctl->desc->pins + i; struct sunxi_desc_function *func = pin->functions; while (func->name) { /* Create interrupt mapping while we're at it */ if (!strcmp( func->name, "irq")) { int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; pctl->irq_array[irqnum] = pin->pin.number; printk(KERN_EMERG"[lmx] pctl- >irq_array[%d] = %d (func->irqnum:%d func->irqbank:%d)\n", irqnum, pin->pin.number, func->irqnum, func->irqbank); } sunxi_pinctrl_add_function(pctl, func->name); func++; } } ...... return 0; } // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define IRQ_PER_BANK 32 ```  It can be found that the index corresponding to PF4(164) is 132, which was originally correctly assigned to 164, but was overwritten to PG4(196). It is not difficult to find that the reason for the overwriting is that the func->irqbank value of PG4 is wrong (4), resulting in an error in the index subscript calculation. According to the context, the correct value of func->irqbank should be 5. Substituting it into the calculation, we get the correct value 164: int irqnum(164) = func->irqnum(4) + func->irqbank(5) * IRQ_PER_BANK(32); There is a high probability that the hardware resource description configuration is incorrect. By searching for the method where irqbank is assigned, we can locate the place where the description configuration is incorrect: ```c // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ { \ .name = "irq", \ .muxval = _val, \ .irqbank = _bank, \ .irqnum = _irq, \ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used. Focus on checking the second parameter: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), NCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI _FUNCTION(0x1, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // 为英文: SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```func->irqbank); } sunxi_pinctrl_add_function(pctl, func->name); func++; } } ...... return 0; } // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define IRQ_PER_BANK 32 ```  It can be found that the index corresponding to PF4(164) is 132, which was originally correctly assigned to 164, but was overwritten to PG4(196). It is not difficult to find that the reason for the overwriting is that the value of func->irqbank of PG4 is wrong (4), resulting in an error in the calculation of the index subscript. According to the context, the correct value of func->irqbank should be 5. Substituting it into the calculation, we get the correct value 164: int irqnum(164) = func->irqnum(4) + func->irqbank(5) * IRQ_PER_BANK(32); There is a high probability that the hardware resource description configuration is incorrect. By searching for the method where irqbank is assigned, we can locate the place where the description configuration is incorrect: ```c // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ { \ .name = "irq", \ .muxval = _val, \ .irqbank = _bank, \ .irqnum = _irq, \ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used. Focus on checking the second parameter: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), NCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI _FUNCTION(0x1, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // 为英文: SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```func->irqbank); } sunxi_pinctrl_add_function(pctl, func->name); func++; } } ...... return 0; } // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define IRQ_PER_BANK 32 ```  It can be found that the index corresponding to PF4(164) is 132, which was originally correctly assigned to 164, but was overwritten to PG4(196). It is not difficult to find that the reason for the overwriting is that the value of func->irqbank of PG4 is wrong (4), resulting in an error in the calculation of the index subscript. According to the context, the correct value of func->irqbank should be 5. Substituting it into the calculation, we get the correct value 164: int irqnum(164) = func->irqnum(4) + func->irqbank(5) * IRQ_PER_BANK(32); There is a high probability that the hardware resource description configuration is incorrect. By searching for the method where irqbank is assigned, we can locate the place where the description configuration is incorrect: ```c // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ { \ .name = "irq", \ .muxval = _val, \ .irqbank = _bank, \ .irqnum = _irq, \ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used. Focus on checking the second parameter: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), NCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI _FUNCTION(0x1, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // 为英文: SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```h #define IRQ_PER_BANK 32 ```  It can be found that the index corresponding to PF4(164) is 132, which was originally correctly assigned to 164, but was overwritten to PG4(196). It is not difficult to find that the reason for the overwriting is that the value of func->irqbank of PG4 is wrong (4), resulting in an error in the calculation of the index subscript. According to the context, the correct value of func->irqbank should be 5. Substituting it into the calculation, we get the correct value 164: int irqnum(164) = func->irqnum(4) + func->irqbank(5) * IRQ_PER_BANK(32); There is a high probability that the hardware resource description configuration is incorrect. By searching for the method where irqbank is assigned, we can locate the place where the description configuration is incorrect: ```c // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ { \ .name = "irq", \ .muxval = _val, \ .irqbank = _bank, \ .irqnum = _irq, \ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used. Focus on checking the second parameter: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), NCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI _FUNCTION(0x1, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // 为英文: SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```h #define IRQ_PER_BANK 32 ```  It can be found that the index corresponding to PF4(164) is 132, which was originally correctly assigned to 164, but was overwritten to PG4(196). It is not difficult to find that the reason for the overwriting is that the value of func->irqbank of PG4 is wrong (4), resulting in an error in the calculation of the index subscript. According to the context, the correct value of func->irqbank should be 5. Substituting it into the calculation, we get the correct value 164: int irqnum(164) = func->irqnum(4) + func->irqbank(5) * IRQ_PER_BANK(32); There is a high probability that the hardware resource description configuration is incorrect. By searching for the method where irqbank is assigned, we can locate the place where the description configuration is incorrect: ```c // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ { \ .name = "irq", \ .muxval = _val, \ .irqbank = _bank, \ .irqnum = _irq, \ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used. Focus on checking the second parameter: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), NCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI _FUNCTION(0x1, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // 为英文: SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```png#pic_center) It can be found that the index corresponding to PF4(164) is 132, which was originally correctly assigned to 164, but was overwritten to PG4(196). It is not difficult to find that the reason for the overwriting is that the value of func->irqbank of PG4 is wrong (4), resulting in an error in the calculation of the index subscript. According to the context, the correct value of func->irqbank should be 5. Substituting it into the calculation, we get the correct value 164: int irqnum(164) = func->irqnum(4) + func->irqbank(5) * IRQ_PER_BANK(32); There is a high probability that the hardware resource description configuration is incorrect. By searching for the method where irqbank is assigned, we can locate the place where the description configuration is incorrect: ```c // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ { \ .name = "irq", \ .muxval = _val, \ .irqbank = _bank, \ .irqnum = _irq, \ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used. Focus on checking the second parameter: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), NCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI _FUNCTION(0x1, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // 为英文: SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```png#pic_center) It can be found that the index corresponding to PF4(164) is 132, which was originally correctly assigned to 164, but was overwritten to PG4(196). It is not difficult to find that the reason for the overwriting is that the value of func->irqbank of PG4 is wrong (4), resulting in an error in the calculation of the index subscript. According to the context, the correct value of func->irqbank should be 5. Substituting it into the calculation, we get the correct value 164: int irqnum(164) = func->irqnum(4) + func->irqbank(5) * IRQ_PER_BANK(32); There is a high probability that the hardware resource description configuration is incorrect. By searching for the method where irqbank is assigned, we can locate the place where the description configuration is incorrect: ```c // drivers/pinctrl/sunxi/pinctrl-sunxi.h #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ { \ .name = "irq", \ .muxval = _val, \ .irqbank = _bank, \ .irqnum = _irq, \ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used. Focus on checking the second parameter: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), NCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI _FUNCTION(0x1, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // 为英文: SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```\ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used, and the second parameter is checked in particular: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // It can be found that the second parameter is exactly 4. According to the analysis results and combined with the context, the correct one should be 5 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```\ } ``` The SUNXI_FUNCTION_IRQ_BANK macro is used, and the second parameter is checked in particular: ```c // drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c static const struct sunxi_desc_pin sun50iw9p1_pins[] = { ...... SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ // It can be found that the second parameter is exactly 4. According to the analysis results and combined with the context, the correct one should be 5 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```/* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```/* PG_EINT5 */ SUNXI_FUNCTION(0x7, "io_disabled")), ...... }; ``` The modified pctl->irq_array prints out correctly:  After actual testing, PF4 can be set to interrupt mode normally. ## Problem summary The PG4 interrupt information description in the SoCs pinctrl driver provided by Allwinner is wrong, resulting in the overwriting of the PF4 pin number. Therefore, the problem can be solved by correcting the PG4 description information. This problem not only affects the unusability of PF4, but also the unusability of the PG4 pin. From the code, if you want to set PG4 to interrupt mode, the actual modification will be PA0(0). ```c --- a/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c +++ b/longan/kernel/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun50iw9p1.c @@ -693,7 +693,7 @@ SUNXI_FUNCTION(0x0, "gpio_ in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ - SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PG_EINT4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), ```

Jacktang

Finding the root cause of the problem by analyzing the source code requires skill.

单子yang

Watch and learn! I think it is well written...Oh...Thank you for sharing!