I recently bought an Antminer T9+ mining card on a certain fish website. The mining era has gradually faded from the public's view, but the mining cards that once worked hard for mining have been sold in large quantities on a certain fish website, and the price is cheap. It is very affordable to buy it as a development board.
The configuration of T9+ mining card is basically very rich, which can meet the needs of beginners. The hardware resources include zynq xc7z010-clg400 dual-core ARM A9 processor, the main frequency can run up to 666.6666MHz, 2 external 512MB DDR3 memory totaling 1GB, 1 2GB NAND Flash, 1 B50612D Gigabit Ethernet PHY interface, a reserved TF card interface, and multiple PL-side I/O expansion. In general, the hardware resources are already considerable, after all, it is only 50 meters.
After getting the T9+, power it on for testing. The default should be NAND Flash boot. If not, you can switch it yourself according to the boot mode configuration pin.
The power supply is input from the 6-pin large white terminal in the lower right corner of the control board. Input 12V power supply. After power-on, the starting current is about 180mA. Use USB to TTL serial port debugger, set the baud rate to 115200, connect the 3-pin pin next to the TF card, and you can see the information printed after startup. The Linux kernel version is relatively low.
Next, use T9+ to build your own development environment, switch the startup mode to JTAG, and use Vivado 2019.2 as the development environment.
New Construction
Select device model xc7z010clg400-1
Create a block
Adding a zynq processor
After adding the zynq processor, you need to configure basic peripherals. Double-click the zynq module, first configure DDR3, select MT41K256M16 for the device model, select 32bit for the data width, and keep the rest as default.
Next, configure the peripherals. First, select nand flash for downloading programs, then select eth0 for network communication, and finally select UART1 for printing debugging information. It should be noted that the level of BANK0 is set to LVCMOS3.3V, and the level of BANK1 is set to LVCMOS2.5V, which is the power supply configuration of the T9+ control board itself.
Enable zynq's GPIO, all IOs are MIO, and EMIO is not used.
In the last configuration step, zynq generates a 100M clock for the PL side.
After completing all the above settings, click OK to exit the configuration interface. Click Run Block Automation to start automatic connection.
Next, add a GPIO control module. Since the PL end of the T9+ control card leads to 4 LED lights, add a GPIO control module to control these 4 LED lights.
Configure the GPIO module, set all directions to output, and set the bit width to 4 bits.
Final connection effect diagram
Then click Save to generate the output file and HDL file, one after the other in sequence.
In the above block, a GPIO control module is added, so you need to add an xdc constraint file in the project file.
After the constraint file is added, generate the bit stream file in Vivado.
After compiling, export the hardware project. When exporting, you need to check the bit file.
Next, start vitis2019.2 and start developing embedded software. First, create a hello world program to test whether the serial port printing is normal.
After clicking finish to create a new project, start building the project and compile the project.
After compiling and receiving without any problems or errors, start downloading the program to the control board, open the serial port debugging assistant, and set the baud rate to 115200. For the mining card T9+, you need to solder the J10 pin, the standard 14pin download and debug port with a 2.0 spacing.
Through the serial port debugging assistant, we can see that hello world has been printed out normally, which means that the Zynq processor and the serial port are working normally. Next, we test the internal RAM of Zynq. Create a new project and select Memory Tests provided by Vitis.
The serial port debugging information is all PASSED, indicating that the internal RAM test has passed. Continue to test DDR3, create a new project, and select the zynq DRAM Tests provided by vitis.
Print information through the serial port debugging assistant, and you can choose the DDR3 test mode, including memory size test, read/write eye diagram test, etc. Here I choose the memory size test, the test size is 1023MB in length, that is, 1G full test, enter 6 in the serial port interface to test the entire memory size.
Test the entire memory space of DDR3. The test results show that there is no problem. Finally, test the network port. The PHY chip on the T9+ control board is B50612D, which is a chip that supports 1000M/100M/10M. Create a new project and use the lwip echo server that comes with vitis.
From the information printed by the serial port, we can see that the network has been automatically negotiated and is working in Gigabit full-duplex mode. The IP address of the T9+ control card is 192.168.1.10, and the port number is 7. Use a laptop to ping the T9+ control board. The IP of the laptop needs to be set in the same network segment. I set it to 192.168.1.20.
The control board can be pinged. The network debugging assistant is used to test the sending and receiving of data. A loopback test is performed in the lwip echo server routine to check what data is received and what is forwarded.
The data transmission and reception test is also normal. It should be noted here that there is no b50612d driver in the lwip driver library of vitis, and you need to manually develop the network port chip driver. Here I have written the driver for the phy chip. You can reply in the background: T9+ to get all the codes of this project, including vivado and vitis projects, and the schematic diagram of the T9+ control board.
I will stop here for today. This is a summary of my first use of the T9+ control board, and also a way to share my learning and development experience with everyone.
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