[Evaluation and experience of Zhongke Yihaiwei EQ6HL45 development platform] + Using the emerging digital circuit design language Chisel to develop FPGA

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[Evaluation and experience of Zhongke Yihaiwei EQ6HL45 development platform] + Using the emerging digital circuit design language Chisel to develop FPGA [Copy link]

 

Using the emerging digital circuit design language Chisel to develop EHiWAY-FPGA

1.1. Chisel Installation (Windows 11)

1. Confirm that Java 8 is installed.

   java -version

   java version "1.8.0_291"

2. Download sbt-1.8.0.zip, scala3-3.2.1.zip.

3. Unzip.

4. Add to PATH environment variable.

   $env:PATH+=”;G:DevToolssbtbin;G:DevToolsscala3-3.2.1bin”

   sbt -version

   sbt version in this project: 1.8.0 sbt script version: 1.8.0

   scala-version

   Scala code runner version 3.2.1 – Copyright 2002-2022, LAMP/EPFL

1.2. HelloLED Example

1. Enter the chisel source code HelloLED.scala

   import chisel3._
   
   class HelloLED extends Module {
           val io = IO(new Bundle {
                   val led = Output(UInt(1.W))
           })
           val CNT_MAX = (50000000 / 2 -1).U;
   
           val cntReg = RegInit(0.U(32.W))
           val blkReg = RegInit(0.U(1.W))
   
           cntReg := cntReg + 1.U
           when(cntReg === CNT_MAX) {
                   cntReg := 0.U
                   blkReg := ~ blkReg
           }
           io.led := blkReg
   
   }
   
   object HelloLED extends App {
     (new chisel3.stage.ChiselStage).emitVerilog(new HelloLED())
   }
   

   PS1: Since the LED on the FPGA development board is lit at a low level, the blkReg initialization value should be changed to 1'b1, that is,

   val blkReg = RegInit(1.U(1.W))
   

2. Input the top file of the project HelloLED_top.v

   Also, since the buttons on the FPGA development board are at a low level when pressed, in order to keep the Scala code simple, add the Verilog source code of the top module to invert the signal. At this time, HelloLED.scala does not need to modify the initial level of the LED, that is, there is no need to follow the changes in the aforementioned PS1.

   module HelloLED_top(
           input sys_clk,
           input sys_rstn,
           output led);
   
           wire h_io_led;
           wire res;
   
           assign led = ~h_io_led;
           assign res = ~sys_rstn;
   
           HelloLED u_HelloLED (
                   .clock(sys_clk),
                   .reset(res),
                   .led( h_io_led )
           );
   
   endmodule
   

3. Enter chisel's build file build.sbt

   scalaVersion := "2.12.13"
   
   scalacOptions++= Seq(
     "-feature",
     "-language:reflectiveCalls",
   )
   
   // Chisel 3.5
   addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.3" cross CrossVersion.full)
   libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.3"
   libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.3"
   

4. Build and generate Verilog

   sbt run

   HelloLED.v will be generated.

1. Add the HelloLED.v generated by Chisel and the HelloLED_top.v we manually entered to the EHiWAY-FPGA project.

2. After synthesis and compilation, the FPGA project construction process is completed, and the code stream file is generated and downloaded

3. Operation effect:

lugl4313820

Thanks for sharing, and I look forward to continuing the excitement!