[Sipeed Gaoyun GW2A FPGA development board]——Sipeed official website Tang-Primer-20K development board routine learning

mars4zhu · Published on 2022-11-22 00:23

[Sipeed Gaoyun GW2A FPGA development board]——Sipeed official website Tang-Primer-20K development board routine learning [Copy link]

This post was last edited by mars4zhu on 2022-11-22 01:35

3.Tang-Primer-20K_Examples_Notes

3.1.assign-led-on

I followed the instructions on the Sipeed website step by step. I didn't pay attention the first time. When I saw there were 6 LED lights, I directly wrote the assign statements for 6 LEDs in Verilog.

module assign_led_on(
    output wire [5:0] led_voltage_level
);
    assign led_voltage_level = 6'b010101 ;
endmodule

After comprehensive approval, the corresponding IO constraints are given according to the schematic diagram when constraining.

IO_LOC "led_voltage_level[5]" L16;
IO_PORT "led_voltage_level[5]" PULL_MODE=UP DRIVE=8;
IO_LOC "led_voltage_level[4]" L14;
IO_PORT "led_voltage_level[4]" PULL_MODE=UP DRIVE=8;
IO_LOC "led_voltage_level[3]" N14;
IO_PORT "led_voltage_level[3]" PULL_MODE=UP DRIVE=8;
IO_LOC "led_voltage_level[2]" N16;
IO_PORT "led_voltage_level[2]" PULL_MODE=UP DRIVE=8;
IO_LOC "led_voltage_level[1]" A13;
IO_PORT "led_voltage_level[1]" PULL_MODE=UP DRIVE=8;
IO_LOC "led_voltage_level[0]" C13;
IO_PORT "led_voltage_level[0]" PULL_MODE=UP DRIVE=8;

However, an error occurs during the layout and routing phase, and the error message indicates that the two pins specified in the led_voltage_level[0]/led_voltage_level[1] constraints are dedicated pins and cannot be placed on the pins.

ERROR  (PR2028) : The constrained location is useless in current package
ERROR  (PR2017) : 'led_voltage_level[1]' cannot be placed according to constraint, for the location is a dedicated pin (READY)
ERROR  (PR2028) : The constrained location is useless in current package
ERROR  (PR2017) : 'led_voltage_level[0]' cannot be placed according to constraint, for the location is a dedicated pin (DONE)

A closer look reveals that these two pins are FPGA configuration related pins. After a closer look, it is found that these two pins are dual-function pins, which can be used for configuration DONE and READY signals as well as regular IO. They need to be set in Project->Configuration as follows:

Then perform layout and routing to pass and generate the correct FPGA configuration bitstream file.

After that, just follow the tutorial process to complete the configuration download.

After running the actual Verilog code, the expected effect is in line with the expected effect, that is, LED lights 1/3/5 are lit, as shown in the figure:

PS: Gowin's development environment GOWIN FPGA Designer is so fast in synthesis and layout and routing. It basically completes the whole process from synthesis-layout-routing-timing analysis-power analysis-bitstream generation in a few seconds, which makes people who have been using Quartus and Vivado completely unable to react.

PS1: Note that in the dual-function pin setting window, you can also set JTAG, SSPI, MSPI and other functional pins as regular IO pins, especially JTAG. Once it is configured as regular IO and written to Flash, the JTAG function will no longer be available after power-on-loaded to FPGA-run. At this time, the JTAG debugger cannot find the FPGA chip, and the configuration/download and debugging functions are invalid. You need to follow the solutions to the "Common Problems" in the tutorial ( https://wiki.sipeed.com/hardware/zh/tang/tang-primer-20k/examples/assign_led.html#%E6%88%90%E5%8A%9F%E7%83%A7%E5%BD%95%E8%BF%87%E4%B8%80%E6%AC%A1%E5%A4%96%E9%83%A8-Flash-%E5%90%8E-Programmer-%E8%BD%AF%E4%BB%B6%E6%97%A0%E6%B3%95%E5%86%8D%E7%83%A7%E5%BD%95），即短接FLASH引脚，使得FPGA无法正常加载Flash中的配置文件，此时FPGA的JTAG功能正常，从而再次进行配置/下载、调试功能。

3.2.key-led-on

3.2.1. Error in the official website routine code

According to the tutorial settings, I found that after downloading the code and running it, the LED did not light up as expected when the key was pressed. I carefully checked the settings and found no difference compared with the example instructions. Finally, I found that there was a problem with the example code. The source code is as follows:

module key_led_on(
    input key,
    output [5:4] led
);
    assign led[1:0] = {2{key}};
endmodule

Screenshot as evidence:

The code in Tools->Schematic Viewer shows that there is no connection between the LED and the key, as shown in the figure:

3.2.2. Modify the Verilog code

module key_led_on(
    input key,
    output [5:4] led
);
    assign led[5:4] = {2{key}};
endmodule

The modified code is displayed as follows in Tools->Schematic Viewer:

The final running effect is the same as the website routine.

3.2.3. Further optimize the code, each key corresponds to each LED

In order to achieve a one-to-one correspondence between key and LED, the code is further optimized as follows:

IO_LOC "led[5]" L16;
IO_PORT "led[5]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[4]" L14;
IO_PORT "led[4]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[3]" N14;
IO_PORT "led[3]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[2]" N16;
IO_PORT "led[2]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[1]" A13;
IO_PORT "led[1]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[0]" C13;
IO_PORT "led[0]" PULL_MODE=UP DRIVE=8;
IO_LOC "key[4]" C7;
IO_PORT "key[4]" PULL_MODE=UP;
IO_LOC "key[3]" D7;
IO_PORT "key[3]" PULL_MODE=UP;
IO_LOC "key[2]" T2;
IO_PORT "key[2]" PULL_MODE=UP;
IO_LOC "key[1]" T3;
IO_PORT "key[1]" PULL_MODE=UP;
IO_LOC "key[0]" T10;
IO_PORT "key[0]" PULL_MODE=UP;

At the same time, modify the IO constraint file as follows:

module key_led_on(
    input wire [4:0] key,
    output wire [5:0] led
);
    assign led[4:0] = key[4:0];
    assign led[5] = 1'b0;
endmodule

And you also need to set the corresponding SSPI, DONE, and READY dedicated pins to regular IO pins in the corresponding Project->Configuration setting window.

The running effect is as shown in the figure:

PS: In the Programmer, if you click Cancel when the SRAM Program is in progress, the FPGA will be reset and waiting for downloading. It will not run the new code or the original code.

PS1: After reporting this issue to the administrator in the Sipeed-FPGA official QQ group on 2022-11-21, the issue was corrected in a timely manner. The official website routine code has been corrected.

3.3.decode-led-on

Just follow the website routine.

3.4.blink-led

Just follow the website routine.

3.5. flow-led (official website is not available yet, please fill in the blank yourself)

A counting register is implemented internally, which adds 1 on the rising edge of the input clock signal, returns to zero after accumulating to 27_000_000, and then restarts counting, and so on. Then, each time the highest count is accumulated, the LED is cyclically shifted left by 1 bit. The Verilog code is as follows:

module flow_led (
        input  sys_clk,
        input  sys_nrst,

        output  [5:0] led
);

        parameter COUNTER_MAX = (27_000_000-1);

        reg [31:0] rCounter;
        always @ (posedge sys_clk or negedge sys_nrst) begin
                if (!sys_nrst) begin
                        rCounter <= 32'd0;
                end
                else begin
                        rCounter <= (rCounter >= COUNTER_MAX) ? 32'd0 : (rCounter + 32'd1);
                end
        end
// ============================

        reg [7:0] rLED;
        always @ (posedge sys_clk or negedge sys_nrst) begin
                if (!sys_nrst)
                        rLED <= 8'b0000_0001;
                else
                        rLED[7:0] <= (rCounter == COUNTER_MAX) ?
                                {rLED[6:0], rLED[7]} : rLED;
        end

// ============================
        assign led = ~rLED[5:0];

endmodule

The IO constraint files are as follows:

IO_LOC "led[5]" L16;
IO_PORT "led[5]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[4]" L14;
IO_PORT "led[4]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[3]" N14;
IO_PORT "led[3]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[2]" N16;
IO_PORT "led[2]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[1]" A13;
IO_PORT "led[1]" PULL_MODE=UP DRIVE=8;
IO_LOC "led[0]" C13;
IO_PORT "led[0]" PULL_MODE=UP DRIVE=8;


IO_LOC "sys_nrst" T10;
IO_PORT "sys_nrst" PULL_MODE=UP;

IO_LOC "sys_clk" H11;
IO_PORT "sys_clk" PULL_MODE=UP;

You need to set the SSPI, DONE, and READY dedicated pins to regular IO pin functions in Project->Configuration, as mentioned above, so I won’t repeat it here.

The running effect is as shown in the figure:

PS:

Circular left shift: rLED[7:0] <= {rLED[6:0], rLED[7]}; After this code runs, the LED lights up in a circular flow.
Fill with zero and shift left: rLED[7:0] <= rLED << 1; After running, the LED has only one running light effect, and all LEDs are turned off after overflow.

nmg · Published on 2022-11-22 11:09

The comprehensive development environment and fast layout and routing are indeed a major feature of Gaoyun. Netizens who have previously evaluated Gaoyun FPGA also praised its speed.