Xianji official dry goods: HPM6750 dual-core routine experience and multi-core debugging

谍纸天眼

Xianji official dry goods: HPM6750 dual-core routine experience and multi-core debugging [Copy link]

 

HPM6750 from Pioneer Semiconductor integrates two RISC-V processors with a main frequency of up to 816MHz. Since there are two CPUs, why should we waste them? This article will show you how to try the dual-core routine and experience the lightning-fast feeling brought by the dual engines.

HPM6750 dual-core adopts master-slave structure, CPU0 and CPU1 use the same configuration:

● Support the same instruction set

● L1 instruction and data caches of the same size

● Equal size instruction and data local memory: 256 KB ILM and 256 KB DLM

CPU0 and CPU1 use the same memory map with the following exceptions:

● The CPU's own instruction/data local memory ILM/DLM is private;

● FGPIO is private

● The platform interrupt controller PLIC is private

● The software interrupt controller PLICSW is private

● The machine timer MCHTMR is private

CPU0 and CPU1 use the same privilege mode setting.

CPU0 is the master CPU and CPU1 is the slave CPU. When a reset occurs, the system is always started by CPU0, and CPU1 is in standby mode. When necessary, CPU0 loads the program image of CPU1 and then releases CPU1. The steps are as follows:

1. CPU0 writes the code mirror address of CPU1 into the SYSCTL_CPU1_GPR0 register

2. CPU0 writes the CPU1 startup code into the SYSCTL_CPU1_GPR1 register, the code is 0xC1BEF1A9

3. CPU0 clears the SYSCTL_CPU1_LP [HALT] bit to 0 to release CPU1

The steps for developing a dual-core application are as follows:

according to

The README_zh.md file in "E:\sdk_env_v0.9.0\hpm_sdk\samples\multicore\hello" is as follows:

The multi-core example project runs the "hello word" example on Core0 and the "rgb_led" example on core1.

In this project:

- The serial port outputs "hello world"; manually input string information on the keyboard and print it out through the serial port

- RGB LED will switch between red, green and blue in sequence

## Hardware Setup

BOOT_PIN should be set to: 0-OFF, 1-OFF

## Generate and compile multi-core project

In this example: the core0 example is executed in FLASH, and the core1 project is executed in ILM.

The user must first generate and compile the __Core1__ project

Users must generate and compile the __Core0__ project after generating and compiling the core1 project.

### Generate core1 project

__CMAKE_BUILD_TYPE__ must be one of the following options:

- *"sec_core_img"*

- *"sec_core_img_release"*

If you use the SDK env package to generate the project, you need to use *"-t sec_core_img"*

### Generate core0 project

__CMAKE_BUILD_TYPE__ Unrestricted

## Operation phenomenon

- Download the core0 example to the device and run it

- Download the core1 example to the device and run it

In this article, referring to the above instructions, we will create new FreeRTOS-related programs in core0 and core1 respectively, that is, run RTOS on each of the two cores.

Create a new SES project for Core1 program

Copy the freertos_hello example project under the HPM 6750 SDK folder "sdk_env_v0.9\hpm_sdk\samples\rtos" to "sdk_env_v0.9.0\hpm_sdk\samples\multicore\hello\" and rename it to "FreeRTOS_RISCV1".

Modify the configuration in the CMakeLists.txt file and add the link file of core1, as shown in the following figure:

Then follow the steps in the SDK Development Guide "HPM6750EVKMINI_UG" to generate the project files for Segger Embedded Studio. To generate the project with the SDK env package, you need to add "-t sec_core_img"*

Create a new SES project for the Core0 program

Copy the freertos_hello example project under the HPM 6750 SDK folder "sdk_env_v0.9\hpm_sdk\samples\rtos" to "sdk_env_v0.9.0\hpm_sdk\samples\multicore\hello\" and rename it to "FreeRTOS_RISCV".

Modify the configuration in the CMakeLists.txt file and add the link file of core0, as shown in the following figure:

Then generate the project files of Segger Embedded Studio according to the project generation steps in the SDK development guide document "HPM6750EVKMINI_UG".

SES project for compiling Core1 program

Because the core0 program depends on the source files compiled and converted by the core1 project, the core1 project must be compiled before compiling the core0 program.

SDK will generate the project file FreeRTOS_RISCV in the FreeRTOS_RISCV\hpm6750evkmini_build\segger_embedded_studio file path. By double-clicking the file, you can directly enter SES (segger embedded studio), open the project, and then compile.

After the core1 project is compiled, the file "sec_core_img.c" will be generated and automatically copied to the core0 project path FreeRTOS_RISCV/src/. In the core1 FreeRTOS routine, the RGBLED is mainly lit up in sequence.

SES project for compiling Core0 program

The FreeRTOS routine of core0 mainly completes RTOS multi-tasking operation.

First, add a processing interface for loading from the core image to the core0 project.

And place this interface after board_init

Multi-core debugging

When debugging a dual-core program, first download and start the core0 program.

First press F5 in the SES project of core0 to run the program of the core0 main core; then press F5 in the SES project of core1 to run the program of core1.

It can be seen that core0's program tasks 1 and 2 can be executed in turn, and the IDLE task can be scheduled for execution during their sleep periods.

Slightly adjust the above code to adjust the delay time of task 1 and task 2, where task 2 is no longer delayed.

in conclusion

HPM6750 uses dual RISC-V cores, which can easily adapt to various interfaces of the master core and slave core, and can fully and flexibly utilize various resources of the SoC. It provides a more friendly experience for applications with high real-time requirements and diverse control content.

nmg

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lugl4313820

HPM6750 uses dual RISC-V cores, which can easily adapt to various interfaces of the master core and slave core, and can fully and flexibly utilize various resources of the SoC. It provides a more friendly experience for applications with high real-time requirements and diverse control content.

Can I run Ubuntu?

hustjtj0806

lugl4313820 Published on 2022-10-28 20:46 HPM6750 uses dual RISC-V cores, which can easily adapt to various interfaces of the master core and the slave core, and can fully and flexibly utilize various resources of soc. To implement...

Definitely not.

tuu

Following these steps does not allow core1 to run or is there something wrong with my operation?