Cadence Certus Closure Solution is a new generation chip-level convergence solution. Welcome to learn more!

eric_wang

Cadence Certus Closure Solution is a new generation chip-level convergence solution. Welcome to learn more! [Copy link]

Efficiently complete chip-level signoff convergence, accelerate chip generation and time to market

Cadence Certus Closure Solution is the industry's first fully automated, large-scale distributed environment for full-chip optimization and signoff. It can speed up chip-level simultaneous optimization and signoff by up to 10 times. In addition, the solution supports the high-capacity requirements of advanced designs for instance units with no capacity restrictions. It uses a new architecture based on massively parallel technology to support true fully automated, large-scale distributed hierarchical full-chip optimization and signoff convergence.

The large-scale distributed computing capabilities of Cadence Certus Closure Solution can simultaneously support full-chip optimization and implementation in Innovus Implementation System, metal filling in Pegasus Physical Verification System, parasitic parameter extraction with Quantus Extraction Solution, and full static timing analysis with Tempus Signoff Solution. Thanks to the scalable architecture, the highly integrated Integrity 3D-IC solution can be used for the same or different process nodes, millions of instance dies, and achieve distributed large-scale synchronous optimization and signoff.

Core Advantages

A major breakthrough in productivity improvement of 10 times, accelerating design closure and time to market

Key Features

Cloud-ready, fully automated, massively distributed environment for full-chip optimization and signoff

• Massively parallel distributed architecture for simultaneous optimization and sign-off
• Fully automated, massively distributed full-chip flat STA analysis, optimization, routing, parasitic extraction, metal fill, and signoff
• Achieve accurate timing and power closure in accordance with full chip timing signoff requirements
• Shares computing resources with distributed optimization and sign-off convergence, minimizing memory peaks
• Cloud-ready, distributed, tier-optimized and sign-off architecture ideal for cloud and data center environments

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lkh747566933

That's amazing. I only knew that he had a software for drawing schematics and PCBs. And it's so advanced.