Problems with emulating VCD file system tasks

chenbingjy

Problems with emulating VCD file system tasks [Copy link]

I saw an example on page 97 of Xia Yuwen's book. I tried to do it, but it didn't work.

Code:

`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires
wire led;

// assign statements (if any)
LAMP i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led(led),
.rst_n(rst_n)
);

module M;
initial
$display("Displaying in %m");
endmodule

module top;
M m1();
M m2();
M m3();
endmodule

initial
$dumpfile("myfile.dmp");
initial
$dumpvars;
initial
$dumpvars(1,top); //?
initial
$dumpvars(2,top.m1);
initial
$dumpvars(0,top.m1);
initial begin
$dumpon;
#100000 $dumpoff;
end
initial
$dumpall;

endmodule

Prompt error

Actually, there are two sentences with problems

$dumpvars(1,top);

There is another sentence

$dumpall;

Please give me some advice, thank you!

Jacktang

Looking forward to the emergence of experts in the task of emulating VCD file system