The OP
Published on 2022-9-14 11:34
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The information in the link on the first floor says that the screen is an I8080 interface. From your description, it sounds like an RGB interface. If it is the latter, there should be a limit on the clock frequency. For example, the minimum DCLK of my screen cannot be lower than 19.75MHz
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Published on 2022-9-16 20:59
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littleshrimp
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littleshrimp
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4
Published on 2022-9-14 16:05
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This phenomenon only occurs when the speed is slow. There must be something wrong with the program.
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Published on 2022-9-14 21:44
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秦天qintian0303
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Published on 2022-9-14 21:44
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在爱好的道路上不断前进,在生活的迷雾中播撒光引 |
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This post is from FPGA/CPLD
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This post is from FPGA/CPLD
Comments
The information in the link on the first floor says that the screen is an I8080 interface. From your description, it sounds like an RGB interface. If it is the latter, there should be a limit on the clock frequency. For example, the minimum DCLK of my screen cannot be lower than 19.75MHz
Details
Published on 2022-9-16 20:59
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littleshrimp
Currently offline
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This post is from FPGA/CPLD
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This post is from FPGA/CPLD
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