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RFSOC wireless communication development platform [Copy link]

The RFSOC wireless communication development platform is an algorithm evaluation board based on the Zynq UltraScale + RFSoC ZU28DR/48DR main chip (high-speed ADC and DAC are integrated inside the IC), which supports multi-board cascading. It provides a COTS solution that can provide the advantages of RFSoC while more effectively offloading data and enjoying the benefits of COTS: users get the fastest possible deployment while taking advantage of lower cost of ownership, lifecycle support and simplifying future technology insertion.
The product can reduce the complexity of the RF signal processing chain, maximize input/output channel density without sacrificing wide bandwidth and taking advantage of heterogeneous processing capabilities, and has lower power consumption (ADC/DAC components are eliminated, and FPGA-to-analog interface power consumption is eliminated). The Zynq UltraScale+ device provides an ARM Cortex-A53 processing subsystem, UltraScale+ programmable logic and the highest signal processing bandwidth, which can provide a comprehensive RF signal chain to meet the needs of wireless, cable TV access, test and measurement, early warning/radar and other high-performance RF applications.

Size: 240mm*200mm


Specifications

Processor platform: Zynq UltraScale + RFSoC ZU28DR/48DR
Main interfaces

x1 10/100/1000 Ethernet RGMII (RJ45) port (PS side)
x1 Display Port video interface (PS side)
x1 USB 3.0 Port (PS side)
x1 ATX power supply interface (DC +12V)
x1 USB-JTAG/UART debugging interface
x1 JTAG interface
x3 PMOD interface
x1 SPI WIFI_BT board expansion interface
x4 buttons
4-way DIP switch
External synchronous clock port

Storage Structure

PS 4xDDR4 (4GB, 64bit, 2400MT/s)
PL 4xDDR4 (4GB, 64bit, 2666MT/s)
PS 2xQSPI flash (512MB, 8bit) fixed configuration file
PS 1xMicroSD card slot
PS 1xSATA .M2 hard disk expansion interface (6G speed)

High-speed interface

PL x2 QSFP 100G optical ports
PL x1 FMC expansion port
x8 ADC (12-bit, 4.096GSPS) ports (28DR)
x8 DAC (14-bit, 6.554GSPS) ports (28DR)
x8 ADC (14-bit, 5GSPS) ports (48DR)
x8 DAC (14-bit, 10GSPS) ports (48DR)


Test indicators

This post is from FPGA/CPLD

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A rare good thing, thank you for sharing, I will spend some time to study it next   Details Published on 2023-11-1 23:07
 

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Thank you for introducing the RFSOC wireless communication development platform

What do the following graphics mean?

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Jacktang posted on 2022-9-9 07:27 Thank you for introducing the RFSOC wireless communication development platform. What do the following graphics mean?

EVM, 890MHz single tone, Xilinx RF evaluation tool ADC DAC basic indicators, multi-channel synchronization

If you are interested in the product, you can chat privately or call me at 029-84508304

This post is from FPGA/CPLD
 
 
 

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I studied a bit, hehehe…

This post is from FPGA/CPLD
 
 
 

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A rare good thing, thank you for sharing, I will spend some time to study it next

This post is from FPGA/CPLD
 
 
 

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A rare good thing, thank you for sharing, I will spend some time to study it next

This post is from FPGA/CPLD
 
 
 

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