NUC980 is equipped with an external bus interface (EBI) for external devices. EBI supports independent mode and multiplexed mode for address bus and data bus. The address bus supports a maximum address space of 1MB and the data bus supports a maximum width of 16 bits. EBI supports 3 chip select signals, which can directly connect to three external devices, and the 3 chip select signals can set the read and write timing separately.
From the schematic diagram of the NuMaker-IIoT-NUC980 development board, we can see that some signals of the EBI bus are brought out to CON11, including the address bus ADDR[8~10], data bus DATA[0~15], chip select nCS0, read enable nRE, and write enable nWE.
NuMaker-IIoT-NUC980 development board (for testing, you need to solder 2.54mm double-row pins to CON11)
Two USB data cables (one to VCOM, the other to USB0)
Saleae logic logic analyzer (several test lines), CH0~7 connect to EBI_DATA0~7, CH8 connect to EBI_nWE, CH15 connect to EBI_nRE, CH10 connect to EBI_nCS0, CH11~13 connect to EBI_ADDR8~10
Software Environment
RT-Thread Studio
NuWriter
SecureCRT
Test demonstration of module functions
In the RT-Thread Studio environment, create a project based on the NK-980IOT development board. After the project is created, add the relevant initialization code of the ebi bus to the file. The initialization content includes the HCLK clock, ebi module clock enable, and ebi bus IO multiplexing function configuration, as follows:
Then add the nu_pin_ebi_init() function to the nu_pin_init() function.
Create a file, implement the read and write functions of the ebi bus test, and add it to the msh command. The code is as follows:
The program files and development board connections are ready. Open SecureCRT and execute the download program steps. The system starts successfully. You can see that the ebi read and write commands have been added to the Finsh console.
First, connect the EBI_DATA1 signal to the VDD33 signal (other signals are connected to the logic analyzer at the default low level), so that the data on the 8-bit data bus is 0x02;
According to the chip manual, the CS0 address space is defined as 0x60000000~0x600FFFFF, and the address bus uses EBI_ADDR8~10, so 0x60000500 (bit8~10 is b101) is used as the read and write test address;
enter on the Finsh console, you can see that 0x02 is returned, proving that the EBI read data function is successful;
From the read operation waveform captured by the logic analyzer, we can see that CH1-DATA1 is at a high level and the other DATA signals are at a low level, which is correct; CH11~13 is connected to ADDR8~10 signals as b101, which is correct.
Read Timing Analysis
Before performing timing analysis, we first calculate the theoretical time parameters based on the timing diagram in the official manual and the ebi initialization configuration;
1) tASU (nCS active to nRE active), the chip is fixed to 1MCLK, according to the initialization configuration MCLK = HCLK / DIV = 150M /128, so tASU = 0.853us;
2) tACC (nRE active width), according to the initialization configuration is 4MCLK, so tACC = 3.413us;
3) tAHD (nRE deactive to nCS deactive), according to the initialization configuration is 4MCLK, so tAHD = 3.413us;
Then analyze the read operation waveform captured on the logic analyzer. First, at the falling edge of nCS, the address bus is output simultaneously; after 0.875us (tASU) after the falling edge of nCS, nRE has a falling edge; the low level state of nRE continues
3.375us (tACC); 3.438us (tAHD) after nRE rises, nCS rises.
Based on the above analysis, the EBI bus read timing test is basically consistent with the official manual description (the logic analyzer has a certain error in timing due to insufficient sampling frequency).
From the write operation waveform captured by the logic analyzer, we can see that at the rising edge of nWE, the data bus CH0~7-DATA0~7 is b01010101 (0x55), which is correct; CH11~13 is connected to ADDR8~10 signal is b101, which is correct.
Write Timing Analysis
Before performing timing analysis, we first calculate the theoretical time parameters based on the timing diagram in the official manual and the ebi initialization configuration;
1) tASU (nCS active to nWE active), the chip is fixed to 1MCLK, according to the initialization configuration MCLK = HCLK / DIV = 150M /128, so tASU = 0.853us;
2) tACC (nWE active width), according to the initialization configuration is 4MCLK, so tACC = 3.413us;
3) tAHD (nWE deactive to nCS deactive), according to the initialization configuration is 4MCLK, so tAHD = 3.413us;
Then analyze the write operation waveform captured on the logic analyzer. First, at the falling edge of nCS, the address bus is output simultaneously; after 0.875us (tASU) after the falling edge of nCS, nWE has a falling edge; the low level state of nWE continues
3.375us (tACC); 3.438us (tAHD) after nWE has a rising edge, nCS has a rising edge.
Based on the above analysis, the test EBI bus write timing is basically consistent with the official manual description (the logic analyzer has a certain error in timing due to insufficient sampling frequency).
Compared with NUC970, the advantage of NUC980's EBI module is that the EBI module configuration function is simplified and the timing is concise; the disadvantage is that the module function is castrated, the chip select signal is reduced, and the timing configurability is reduced.
提升卡
变色卡
千斤顶
京公网安备 11010802033920号
