When the pull-up and pull-down resistors are not turned on, it is in floating mode. What is the principle that may cause high power consumption?

一沙一世

When the pull-up and pull-down resistors are not turned on, it is in floating mode. What is the principle that may cause high power consumption? [Copy link]

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When the pull-up and pull-down resistors are not turned on, it is in floating mode and the pin voltage is uncertain. The pin voltage in this mode will change from time to time, which may cause high power consumption. As shown in the figure below, how can the unstable pin voltage cause high power consumption?

Also, during analog input, since the pull-up and pull-down resistors do not work, will it also cause high power consumption?

dcexpert

In high impedance state, the pin state is easily changed by external interference, thereby increasing power consumption.

一沙一世

dcexpert published on 2022-5-17 13:51 In high impedance state, the pin state is easily changed by external interference, thereby increasing power consumption.

Thank you very much. The pin is just a wire. Can you be more specific about which internal device changes due to voltage changes that lead to increased power consumption? Thank you

maychang

"As shown in the figure below, how can the unstable voltage of the pin cause high power consumption?"

This needs to be analyzed from the structure of the MOS gate circuit. There is no such circuit in the part of the diagram you posted. To understand why it causes high power consumption, you need to dissect the gate circuit such as 74HC04 to explain it clearly.

一沙一世

maychang posted on 2022-5-17 14:15 "As shown in the figure below, how can the unstable voltage of the pin cause high power consumption?" This needs to be analyzed from the structure of the MOS gate circuit. In your post...

Thank you very much. Please send me the circuit diagram of 74HC04 and analyze it in depth for students. Thank you.

chunyang

In the high impedance state, the external interference signal induced by the IO will cause the MOS tube in the input stage to switch repeatedly, which will increase the power consumption of the subsequent circuit. In essence, it is the charging and discharging process of the gate capacitance of the subsequent MOS tube. This charging and discharging process is provided by the power supply, so it becomes the source of power consumption.

chunyang

During analog input, the structure of the input stage circuit is different and is not high impedance, so the uncontrolled charging and discharging process of the aforementioned subsequent stage circuit does not exist.

maychang

Yishayishi published on 2022-5-17 14:50 Thank you very much. Please send me the circuit diagram of 74HC04 and analyze it in depth for students. Thank you.

I don't know why, I can't post the picture.

I can only tell you where to look for it: "Fundamentals of Electronic Technology. Digital Part. (Kang Huaguang. 5th Edition)" starting from page 77.

一沙一世

chunyang posted on 2022-5-17 15:27 In the high impedance state, the external interference signal induced by the IO will cause the MOS tube in the input stage to switch repeatedly, which will increase the power consumption of the subsequent circuit. Its essence...

Thank you very much. Is there any more detailed information? It would be best if you could provide a link so I can learn from it.

chunyang

Yishayishi published on 2022-5-17 16:47 Thank you very much. Is there any more detailed information? It would be best if you could provide a link so that I can learn from it.

Just go and read the textbook.

vincentc543

Theoretically, the power consumption of a switch MOS is not too high. The high power consumption is caused by the signal processing program at the back end, such as UART input.

Unstable input will cause frequent interrupts in UART processing and significantly increase power consumption.