The third pit of domestic FPGA chip logic analyzer prompts Can not connect to JTAG server

littleshrimp

The third pit of domestic FPGA chip logic analyzer prompts Can not connect to JTAG server [Copy link]

 

Gaoyun's FPGA IDE is very convenient to use and has a very fast speed. I really want to play with this chip, but unfortunately, this kind of thing is very fatal once a problem occurs.

This time, I encountered the error "Can not connect to JTAG server" when using the logic analyzer. I don't know if it is related to the emulator used by the Tang Nano 4K board.

No solution has been found yet.

littleshrimp

The manual shows that it is Gowin USB Cable (FT2CH). The official board uses FTDI chips. My board is a third-party one, and it uses the BL702C_A0-Q2I MCU.

littleshrimp

The problem is solved and the logic analyzer can now be used normally.

Now even if my board is not plugged into the computer, the logic analyzer starts normally.

Not sure which step solved the problem, I first reinstalled the IDE, which would restore the original version using Programmer.

Then I deleted the original .gao file, thinking that this would allow me to open the logic analyzer interface, but at this time there was only a parallel port in the Cable, and I couldn't connect even if I plugged in the board.

Then check Enabl Programmer and scan the device. The device can be found. However, the Cable still has only Parallel Port.

Close this window, create a new .gao file, configure it, synthesize it, do layout and routing, then open this interface again and you will see Gowin USB Cable. Then download the program and click Start to see the corresponding waveform.

annysky2012

According to the steps you said, it is more related to .gao

RyanC

Hi, I would like to ask, has anyone encountered this problem:

The programmer on the logic analyzer scanned the device, but when loading the a0_0.fs file, an error message appeared.

Error: Fs file download failed!

走路也带风

RyanC posted on 2022-5-10 00:29 Big brother, please tell me, have you ever encountered this problem: The programmer on the logic analyzer scanned the device, but loaded the a0_0.fs file...

Hi, have you solved this problem?