Author: Huang Gang, a member of Yibo Technology Expressway Media
You have seen many balanced high-speed serial signals, but have you seen balanced DDR signals? Come, Mr. High Speed will show you!
First, let's review the relevant concepts of high-speed serial signals. We have introduced a lot of reasons why high-speed serial signals need various equalizations in previous articles (many articles). In fact, in summary, when the high-speed signal reaches a certain rate, the attenuation of the link itself will increase sharply. In addition, the influence of ISI (inter-symbol interference) caused by different code types is also becoming more and more serious. These two aspects seriously affect the performance of high-speed serial signals.
Of course, when it comes to the impact, simply put, it makes the eye diagram of the signal open less or even close. The figure below shows the eye diagram result at the receiving end when we add signals of different rates to the same PCB channel. Due to the increasing attenuation of the high frequency of the link, it can be seen that within the transmission range from 1Gbps to 25Gbps, the eye diagram gradually closes from a wide open state.
Therefore, for high-speed signals, various equalization configurations are very necessary. We can generally see several common equalizations configured at the transceiver end of the chip, such as CTLE, FFE, and DFE!
That’s all about the introduction of high-speed signals. Mr. High Speed almost forgot that this article is mainly about DDR simulation!
The previous article also briefly introduced the standard speed of DDR5. Its starting point is basically the ceiling of DDR4, which is 3200Mbps. The median configuration is between 4800Mbps and 6400Mbps. According to the protocol document, the highest speed is currently 8400Mbps.
In the equalization of DDR5, the DFE equalization module at the receiving end is mainly configured. Speaking of DFE equalization, it is nothing more than adding an additional judgment function on the basis of linear equalization such as FFE.
By carefully reading the DDR5 protocol, we can see that the standard configuration of DDR5 data signals is a 4tap DFE module.
Well, the protocols and theories are too boring, so let's talk about simulation. Let's get the DDR5 model directly and simulate how DFE equalization helps the data signal.
First, we extract a data signal from a real link and build the transceiver model, as shown below:
We can see that the DDR5 particle model does have the AMI algorithm, which means that the DFE module is configured in the receiving model. When we open the AMI model, we can see that the DFE module has 4tap equalization parameters that can be adjusted.
Well, here comes the most important part of this article! That is, we transmit different rates on this extracted DDR5 data channel to see the results at the receiving end, especially the results after equalization.
First of all, the rate we give is 3200Mbps, an entry-level DDR5 rate. At this rate, the DDR4 module we made before can also be successfully guaranteed without DFE equalization. From the simulation results of this DDR5 at this rate, it is shown that DFE equalization is not very helpful at this rate, or in other words, DFE equalization is actually not needed at this rate.
Then we increase the rate to 4800Mbps and see the changes before and after equalization at this rate. We can see that at this rate, the result at the receiving end has gradually attenuated, and we can also see that the effect of equalization has gradually become prominent.
Then we increase the rate and raise the data signal rate to 6400Mbps. At this rate, we can clearly see that the eye diagram is basically very small before equalization, but after DFE equalization, the eye diagram is obviously reopened, and the effect is very obvious.
Finally, we raise the rate to the ceiling of the protocol, which is 8400Mbps. This rate has actually exceeded many high-speed serial signals we are familiar with, such as USB3.0, PCIE3.0, etc. Let's take a look at the difference before and after equalization at this rate.
From the simulation results, it is amazing! DFE equalization can actually reopen a basically closed eye diagram, which fully demonstrates the role of DFE equalization, turning decay into magic!
Through the above simulation results, I believe everyone can clearly see that the data transmission rate of DDR5 is indeed possible to reach an amazing level. Friends who are still using DDR3 or DDR4, do you have the urge to upgrade your products to DDR5?
提升卡
变色卡
千斤顶
京公网安备 11010802033920号
