XC7V690T-2FFG1761I Multiboot loading solution

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XC7V690T-2FFG1761I Multiboot loading solution [Copy link]

XC7V690T-2FFG1761I Multiboot loading solution

Hardware Composition

Main chip introduction

The Virtex-7 series is Xilinx's 28nm FPGA. Compared with Kintex-7, Virtex-7 has more logic resources, and GTH supports a transmission rate of up to 13.1Gbps/lane. The Virtex-7 690T resource list is as follows:

Board function indicators

Power consumption evaluation

The power consumption evaluation results are shown in the following figure:

The board has 4 DDR3L chips in total. At a high temperature of 65°C, the total power consumption is estimated to be 3W;

Based on the above data, when the board is powered by +12V, the power chip efficiency is about 85%, so the total input power consumption of the system is about 40W when the ambient temperature is 65℃;

Power supply design

Clock scheme design

Reset scheme design

Multiboot Loading Solution

The Multiboot solution is to place four different programs in the configuration chip, load different programs into the FPGA according to the selection of RS[1:0], and implement the booting of different programs. The hardware connection method is as above.

The FPGA reconfiguration operation is implemented by sending IPROG commands to the configuration module through a dedicated ICAPE primitive. In application design, you only need to instantiate an ICAPE2 primitive in the application to implement the relevant command sequence to implement the MultiBoot feature;

The effect of the IPROG command is similar to the effect of generating a pulse on the PROGRAM_B pin, but the IPROG command does not reset the reconfiguration logic. After the reconfiguration logic in the FPGA receives the IPROG command, the FPGA performs a reset operation, but does not reset the reconfiguration logic, and pulls the INIT_B and DONE pins low. After the FPGA clears all configuration storage, the INIT_B port is pulled high. Finally, the value of the WBSTAR register is used to reconfigure the FPGA.

The IPROG command sequence is implemented through a state machine. There must be at least 8 states in the state machine to generate the entire IPROG command sequence. Otherwise, the IPROG command sequence cannot be generated and the FPGA cannot be reconfigured. In addition, the sending of the IPROG command is executed by the ICAPE2 module. The output timing of the ICAPE2 module is consistent with the output timing of the SelectMAP. The output data format of the SelectMAP is a bit conversion format, so the configuration data needs to be bit converted during the generation of the IPROG command sequence. Here, bit conversion refers to bit conversion within a byte, that is, the most significant bit becomes the least significant bit, and this is used as a rule to swap bits within a byte.

Table 1. IPROG configuration instructions

The "Language Templates" in Vivado can be used to call ICAPE2 primitives, and the same is true for ISE;

IPROG command part of the state machine code part of the sample, note that the multi-configuration code is placed on the old program, not on the updated program, the program is stored starting from address 0 of the Flash; the updated program is stored after the old program. When the system is powered on, the FPGA will access the address 0 of the Flash and check the ICAPE core in the old program to determine whether to load the new program.

After adding the code, merge the two .bit files into one .mcs;

Subsequent operations use RapidIO to write the WBSTAR register in ICAPE to control RS[1:0] to select program versions in different locations.

VPX Interface Definition

P0:

P0	Row G	Row F	Row E	Row D	Row C	Row B	Row A
1	12V	12V	12V	No Pad*
2	12V	12V	12V	No Pad*
3				No Pad*
4	I2C_SCK1	I2C_SDA1	GND		GND	SYSRESET*	NVMRO
5	GAP*	GA4*	GND	3.3V_Aux	GND	I2C_CLK0	I2C_SDA0
6	GA3*	GA2*	GND		GND	GA1*	GA0*
7	TCK	GND	TDO	TDI	GND	TMS	TRST*
8	GND	REF_CLK -	REF_CLK+	GND			GND
Note: 1. VCC_12V : board working power supply; 2. 3.3V_Aux : board auxiliary power supply; 3. I2C_SCK0 /1 , I2C_SDA0/1 : connected to MCU after being driven , and the pull-up resistor is uniformly 4.7K ; 4. SYSRESET* : connected to FPGA; 5. NVMRO : connected to FPGA through pull-up resistor; 6. GA0*~4*, GAP* : connected to FPGA through pull-up resistor; 7. TRST * : connected to GND through pull-down resistor ; 8. REF_CLK-/+ : connected to clock chip ; 9. TCK , TDO , TDI , TMS , GND : FPGA 's JTAG .

P1:

P1	Row G	Row F	Row E		Row D	Row C	Row B		Row A
			Even	Odd			Even	Odd
J1	Row i	Row h	Row g	Row f	Row e	Row d	Row c	Row b	Row a
1	GPIO01	GND	GND-J1	SRIO01_T0-	SRIO01_T0+	GND	GND-J1	SRIO01_R0-	SRIO01_R0+
2	GND	SRIO01_T1-	SRIO01_T1+	GND	GND-J1	SRIO01_R1-	SRIO01_R1+	GND	GND-J1
3	GPIO02	GND	GND-J1	SRIO01_T2-	SRIO01_T2+	GND	GND-J1	SRIO01_R2-	SRIO01_R2+
4	GND	SRIO01_T3-	SRIO01_T3+	GND	GND-J1	SRIO01_R3-	SRIO01_R3+	GND	GND-J1
5	GPIO03	GND	GND-J1	SRIO02_T0-	SRIO02_T0+	GND	GND-J1	SRIO02_R0-	SRIO02_R0+
6	GND	SRIO02_T1-	SRIO02_T1+	GND	GND-J1	SRIO02_R1-	SRIO02_R1+	GND	GND-J1
7	GPIO04	GND	GND-J1	SRIO02_T2-	SRIO02_T2+	GND	GND-J1	SRIO02_R2-	SRIO02_R2+
8	GND	SRIO02_T3-	SRIO02_T3+	GND	GND-J1	SRIO02_R3-	SRIO02_R3+	GND	GND-J1
9	GPIO05	GND	GND-J1	SRIO03_T0-	SRIO03_T0+	GND	GND-J1	SRIO03_R0-	SRIO03_R0+
10	GND	SRIO03_T1-	SRIO03_T1+	GND	GND-J1	SRIO03_R1-	SRIO03_R1+	GND	GND-J1
11	GPIO06	GND	GND-J1	SRIO03_T2-	SRIO03_T2+	GND	GND-J1	SRIO03_R2-	SRIO03_R2+
12	GND	SRIO03_T3-	SRIO03_T3+	GND	GND-J1	SRIO03_R3-	SRIO03_R3+	GND	GND-J1
13	GPIO07	GND	GND-J1	SRIO04_T0-	SRIO04_T0+	GND	GND-J1	SRIO04_R0-	SRIO04_R0+
14	GND	SRIO04_T1-	SRIO04_T1+	GND	GND-J1	SRIO04_R1-	SRIO04_R1+	GND	GND-J1
15	GPIO08	GND	GND-J1	SRIO03_T2-	SRIO03_T2+	GND	GND-J1	SRIO04_R2-	SRIO04_R2+
16	GND	SRIO04_T3-	SRIO04_T3+	GND	GND-J1	SRIO04_R3-	SRIO04_R3+	GND	GND-J1
Description: 1. SRIOxx_T /R0~3-/+ : 4x RapidIO interface connected to FPGA , line rate supports 6.25G ; 2. SRIOxx_T -/+ : FPGA transmission; 3. SRIOxx_R -/+ : FPGA reception; Note: SRIO01_T/R, software can be instantiated as PCIe

P2:

P2	Row G	Row F	Row E		Row D	Row C	Row B		Row A
			Even	Odd			Even	Odd
J2	Row i	Row h	Row g	Row f	Row e	Row d	Row c	Row b	Row a
1	GPIO09	GND	GND-J2	LVDS01_N	LVDS01_P	GND	GND-J2	LVDS00_N	LVDS00_P
2	GND	LVDS03_N	LVDS03_P	GND	GND-J2	LVDS02_N	LVDS02_P	GND	GND-J2
3	GPIO10	GND	GND-J2	LVDS05_N	LVDS05_P	GND	GND-J2	LVDS04_N	LVDS04_P
4	GND	LVDS07_N	LVDS07_P	GND	GND-J2	LVDS06_N	LVDS06_P	GND	GND-J2
5	GPIO11	GND	GND-J2	LVDS09_N	LVDS09_P	GND	GND-J2	LVDS08_N	LVDS08_P
6	GND	LVDS11_N	LVDS11_P	GND	GND-J2	LVDS10_N	LVDS10_P	GND	GND-J2
7	GPIO12	GND	GND-J2	LVDS13_N	LVDS13_P	GND	GND-J2	LVDS12_N	LVDS12_P
8	GND	LVDS15_N	LVDS15_P	GND	GND-J2	LVDS14_N	LVDS14_P	GND	GND-J2
9	GPIO13	GND	GND-J2	LVDS17_N	LVDS17_P	GND	GND-J2	LVDS16_N	LVDS16_P
10	GND	LVDS19_N	LVDS19_P	GND	GND-J2	LVDS18_N	LVDS18_P	GND	GND-J2
11	GPIO14	GND	GND-J2			GND	GND-J2
12	GND			GND	GND-J2			GND	GND-J2
13	GPIO15	GND	GND-J2			GND	GND-J2
14	GND	RS422_T00-	RS422_T00+	GND	GND-J2	RS422_R00-	RS422_R00+	GND	GND-J2
15	GPIO16	GND	GND-J2	GBE_B-	GBE_B+	GND	GND-J2	GBE_A-	GBE_A+
16	GND	GBE_D+-	GBE_D+	GND	GND-J2	GBE_C-	GBE_C+	GND	GND-J2

Jacktang

The XC7V690T-2FFG1761I Multiboot introduced by the OP is quite clear to load, save it for later use

VCC135

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