TDC - Time to Digital Converter

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TDC - Time to Digital Converter [Copy link]

When using the delay chain in FPGA to implement tdc, when latching the output data of the delay chain, the input data change near the clock edge violates the setup and hold time of the trigger, causing the trigger to enter a metastable state. I wonder if any great god can teach me how to deal with this metastable state! It's really urgent~

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Can someone please take a look at this? I've been thinking about it for a week and still can't solve it. Please save the child.

Jacktang

Many people talk about this

The principle of metastable state is not described here. You can refer to it when directly pasting the method to implement tdc:

Synchronize asynchronous signals
By delaying two cycles, the signal is extracted through multi-level register edges.

input    sig_synq;
wire     sig_synq_o;
reg[3:0] sig_synq_r;

always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
		sig_synq_r <= 4'd0;
	else
		sig_synq_r  <={sig_synq_r[2:0],sig_synq};
end

assign sig_synq_o = sig_synq_r[2] & ~sig_synq_r[3];

Asynchronous reset, synchronous release

input    rst_n
wire 	 synq_rst_n;
reg[1:0] rst_n_r;

always@(posedge clk or negedge rst_n)begin
	if(~rst_n) rst_n_r <= 2'd0;
	else       rst_n_r <= {rst_n_r[0],1'd1};
end 

assign synq_rst_n = rst_n_r[1];

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Jacktang published on 2021-8-22 22:15 Many people have talked about the principle of metastable state. I will not elaborate on it here. You can refer to the method to implement tdc directly: Asynchronous signal synchronization communication...

In this case, the signal is aligned with the rising edge of the clock, and TDC cannot measure the time information.

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Jacktang published on 2021-8-22 22:15 Many people have talked about the principle of metastable state. I will not elaborate on it here. You can refer to the method to implement tdc directly: Asynchronous signal synchronization communication...

Senior, are you talking about processing the input signal or the data processed by TDC? Due to my lack of ability, I don't quite understand. Can you explain it in more detail?

Jacktang

FPGA Rookie posted on 2021-8-23 14:35 Senior, are you talking about processing the input signal or the data processed by TDC? Due to my own lack of ability, I don’t quite understand it. Please trouble the senior...

This is hard to explain.

If FPGA implements TDC measurement by time interpolation, it can be implemented by using logic carry chain or clock phase interpolation. Clock phase interpolation is simpler to implement, but the accuracy is limited by the number of clocks with shifted phases, and it may enter a metastable state.

There are a few posts

https://en.eeworld.com/bbs/thread-465445-1-1.html
https://en.eeworld.com/bbs/thread-247457-1-1.html
https://bbs.eeworld. com.cn/thread-471474-1-1.html

Please read the relevant information for details.

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Jacktang posted on 2021-8-23 15:44 This is hard to explain. If FPGA implements TDC measurement using time interpolation, it can be achieved using both the logical carry chain and the clock phase interpolation method...

Okay, thank you senior!

Demons000321

Hello, I am also working on TDC recently and have also encountered the problem of metastable state. Did you solve it in the end? How did you solve it?