Super summary: 25 op amp parameters explained in detail
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1. Input bias current and input offset current
Generally, the datasheet of an op amp lists many op amp parameters. Some are easy to understand and we often pay attention to them, but some may be overlooked. In the following topics, each parameter will be explained and analyzed in detail. We strive to explain the op amp parameters clearly in terms of principles and their impact on applications. Due to my limited level, there are inevitably some omissions in the blog post. I hope everyone will criticize and correct me. (Some pictures in the article may be out of date)
The first section will explain the input bias current Ib and input offset current Ios of the op amp. As we all know, an ideal op amp has no input bias current Ib and input offset current Ios. But every actual op amp has input bias current Ib and input offset current Ios. We can use the model in the figure below to explain their definitions.
The input bias current Ib is due to the existence of leakage current (let's call it leakage current) at both input poles of the op amp. We can understand that each input terminal of the ideal op amp is connected in series with a current source, and the current values of these two current sources are generally different. In other words, in actual operation, there will be current flowing into or out of the input terminal of the op amp (not quite the same as the virtual disconnection of the ideal op amp). Then the input bias current is defined as the average value of these two currents, which is easy to understand. The input offset current is defined as the difference between the two currents.
After the definition, let's take a deeper look at the source of this current. Then we have to look at the input stage of the op amp. The input stage of the op amp generally uses differential input (voltage feedback op amp). The tube used is either a triode bipolar or a field effect tube FET. As shown in the figure below, for bipolar, in order to make it work in the linear region, it is necessary to provide a bias voltage to the base, or to have a relatively large base current, that is, it is often said that the triode is a current control device. Then its bias current comes from the base current of the triode in the input stage. Since it is difficult to achieve complete matching of the two tubes in the process, there is always a little difference in the base current of the two tubes Q1 and Q2, which is the input offset current. The two values of the bipolar input op amp are still considerable, that is to say, they are relatively large, and they must be considered when designing the circuit. For the FET input op amp, since it is a voltage-controlled current device, it can be said that its gate current is very small, generally in the fA level, but unfortunately, each of its input pins has a pair of ESD protection diodes. Both diodes have leakage current, which is generally much larger than the gate current of the FET, and this also becomes the source of the bias current of the FET input op amp. Of course, the two pairs of ESD protection diodes cannot be completely consistent, so there are different leakage currents, and the difference in leakage current constitutes the main component of the input offset current.
The upper table in the following list shows the input bias current and input offset current of the bipolar LM741. This current flows to the external resistor, even if it is a K-ohm resistor, it will generate an offset voltage of tens of uV. After amplification, it is easy to make the output voltage error reach the mV level. The lower table shows the input bias current and input offset current of the CMOSFET OPA369. These two values are much smaller. The typical values of the input bias current and input offset current of a better COMS op amp can achieve the goal of less than 1pA.
It should also be emphasized here that the reverse leakage current of ESD is related to its reverse voltage. Therefore, when Vin=(Vcc-Vss)/2, the voltages applied to the two ESD protection diodes are equivalent, and their reverse currents can be considered to be approximately equal. At this time, the ideal situation is that there is no current flowing in or out, and the actual situation is that the current reaches the minimum value. Therefore, there is a minimum bias current at this time. When the voltage Vin at the input of the op amp is not equal to (Vcc-Vss)/2, it is bound to cause the reverse voltage of one diode to be high and the other to be low. At this time, the reverse leakage currents of the two diodes are not equal, and this difference current will constitute the main component of the input bias current. This scene is called the collar effect. Therefore, to minimize the FET input bias current, the common mode voltage must be set at (Vcc-Vss)/2.
The definition and source are analyzed above. Now let's talk about the impact of these two parameters on the circuit. The input bias current will flow through the external resistor network, thereby converting into the offset voltage of the op amp, and then reaching the output terminal of the op amp after passing through the op amp, causing the input error of the op amp. This also explains why, in the reverse amplifier circuit, a resistor should be connected to the non-inverting input terminal of the op amp and then grounded. And this resistor should be equal to the value of the reverse input terminal resistor and the feedback resistor in parallel. This is to make the voltage values formed when the bias currents of the two input terminals flow through the resistors equal, so that the offset voltage they introduce is 0. This is too abstract, it is easier to understand by looking at the following set of pictures.
Another point is that for circuits that detect tiny currents, which are generally transimpedance amplifier circuits, such as photodiode detection circuits, the useful light signals are generally weaker, and the converted light power signals are even weaker, often in the nA level or even pA level. The original intention of this circuit is to allow the photocurrent to flow to the feedback resistor to generate a voltage at the output of the amplifier circuit. If the input bias current of the selected op amp is too large, part of this weak photocurrent will flow into the input of the op amp, and the preset I/V linear conversion cannot be achieved.
Another point to note is that the input offset current of many op amps will change with temperature. As shown in the figure below, the input offset current of OPAl350 will increase rapidly above 25 degrees. The input bias current at 100 degrees is several hundred times that at 25 degrees. If the system is designed to work in a wide temperature range, this factor must be considered.
The above is a long-winded discussion of the input bias current and offset current of the op amp. I hope it is useful to everyone. In the next section, other parameters will be analyzed in detail.
2. How to measure input bias current Ib and offset current Ios
The previous section talked about op amp input bias current and input offset current. This section gives the input bias current measurement method. Generally speaking, there are two main testing methods. One is to let the input bias current flow into a large resistor to form an offset voltage, then amplify the offset voltage and measure it, so that the input bias can be calculated in reverse; the other method is to let the input bias current flow into a capacitor and use the capacitor to integrate this current. In this way, as long as the voltage change rate on the capacitor is measured, the bias current of the op amp can be calculated.
Let's first introduce the first method. The specific circuit is shown in the figure below. C1 is the advance compensation capacitor to prevent the circuit from oscillating. It should be selected according to the actual circuit. OP2 is the test auxiliary amplifier. It is necessary to select an amplifier with low bias voltage and low bias current. The test steps and principles are calculated step by step below.
( 1) First, test the offset voltage of the op amp. Close S1 and S2, test the output voltage of the OP2 op amp and record Vout. Then the input offset voltage is:
( 2) Open S2, and the Ib+ of the op amp to be tested flows into R2, which will form an additional offset voltage Vos1. Test the output voltage of the OP2 op amp and record it as Vout1. Then the op amp's same-direction input offset voltage is:
( 2) Close S2 and open S1. The Ib- of the op amp to be tested flows into R1, which will form an additional offset voltage Vos2. The output voltage of the OP2 op amp is tested and recorded as Vout2. Then the op amp reverse input offset voltage is:
( 4) The op amp input bias current is
Ib=[(Ib+)+(Ib-)]/2
The input offset current of the op amp is
Ios=(Ib+)-(Ib-)
This test method has several disadvantages. One is that it uses very large resistors R1 and R2, which are usually M ohm level. These two resistors introduce a lot of voltage noise. Due to the resistance value of resistors R1 and R2, it is difficult to measure the bias current of the FET input op amp.
The second method is to let the input bias current of the op amp flow into the capacitor. The specific test is shown in the figure below. It is easy to understand the principle of the test from the formula in the figure. The key to this test is to select a capacitor with very small leakage current.
(1) Open S1, IB+ flows into capacitor C, and use an oscilloscope to observe the changes in Vo. The result is shown in the figure below. IB+ can be calculated using the method in the figure above.
(2) Close S1 and open S2. IB- flows into capacitor C. Use an oscilloscope to observe the changes in Vo. The results are shown in the figure below. IB- can be calculated.
(3) Based on the definition, the input bias current and offset current of the op amp can be calculated.
This test method can measure the offset current of fA level. When testing, it is necessary to select capacitors with low leakage current. It is recommended to use Teflon capacitors, polypropylene (PP) capacitors or polystyrene capacitors with extremely low leakage current.
Another experience I want to share is that during the soldering process of chip capacitors, impurities such as solder paste may remain on the pins, which will greatly increase the leakage current of the FET op amp. I once tested an op amp with a bias current of less than 10pA. Because the pins were not cleaned, the measured results showed a large error, or error, reaching the nA level.
3. Input offset voltage Vos and temperature drift
In the application of op amps, it is inevitable to encounter the input offset voltage Vos of the op amp, especially when amplifying DC signals. Due to the existence of the input offset voltage Vos, the output end of the amplifier circuit will always add unexpected errors. To give a simple, old-fashioned, and classic example, due to the existence of the input offset voltage, our electronic scale will display the weight before it is adjusted and before anything is put in. We don't always want the weight we buy to be different from the actual weight. It's okay to buy an apple, but if you buy a platinum ring, a difference of one gram is a lot of money. The following introduces the offset voltage of the op amp and its calculation. Finally, some low input offset voltage op amps will be introduced. If there are any shortcomings, please give me more bricks.
Ideally, when the input voltages of the two input terminals of the op amp are the same, the output voltage of the op amp should be 0V, but the actual situation is that even if the voltages of the two input terminals are the same, the amplifier circuit will have a small voltage output. As shown in the figure below, this is caused by the input offset voltage of the op amp.
Of course, the strict definition should be that in order to make the output voltage of the op amp equal to 0, a small voltage must be added to the two input terminals of the op amp. This small voltage that needs to be added is the input offset voltage Vos. Note that it is the input voltage that is added to make the output voltage equal to 0, rather than the output offset voltage divided by the gain (a small difference) when the input is the same.
The input offset voltage of the op amp comes from the mismatch between the two tubes in the differential input stage of the op amp. As shown in the figure below. Due to the limitation of the process level, this mismatch is inevitable. The mismatch of the differential input stage is a bad boy, and it will cause many other problems, which will be introduced later.
I once consulted a senior op amp design engineer. According to him, the matching degree of two tubes is proportional to the square root of the area of the tube within a certain range, which means that the matching degree is doubled. The area needs to be increased four times. When it reaches a certain level, even if the area is increased, the matching degree will not be improved. Increasing the area will increase the cost of the IC. So there is a commonly used method, which is to test the op amp after it is produced, and then trim it (which can be understood as adjustment). In this way, the accuracy of the op amp can be greatly improved. Of course, testing and trimming both cost money. So the price of precision op amps is relatively expensive. This paragraph is just a casual chat, haha.
We pay attention to the input offset voltage because it will cause errors in the amplifier circuit. The following is to analyze the errors it brings. Before calculation, let's know another parameter that makes us uncomfortable, the temperature drift of the offset voltage, that is, the input offset voltage mentioned above will change with the change of temperature. However, the application environment temperature of our actual circuit is always changing, which brings us a tricky problem. The following table is the parameters intercepted from the OPA376 datasheet. Its maximum temperature drift is 1uV/℃ (-40℃ to 85℃). The Vos of a large number of op amps conform to the normal distribution, so the datasheet generally also gives a histogram of the offset distribution.
When the temperature changes, the input offset voltage drift is defined as:
I just forgot another important parameter, which is the long-term drift of the op amp input offset voltage, which is generally given in terms of uV/1000hours or uV/moth, etc. Some datasheets will give this parameter.
The following example calculates the maximum offset voltage of OPA376 at 85°C. It mainly consists of two parts: one is the input offset voltage at 25 degrees, and the other is the offset voltage drift caused by temperature change.
The specific steps are shown in the figure below. From the results, it seems that the 1uV/℃ temperature drift becomes the dominant factor of the error when multiplied by the temperature change. Therefore, if the designed circuit is used in a wide temperature range, special attention should be paid to the temperature drift.
Vos(85℃)= 25uV+60uV=85uV.
If the gain of the amplifier circuit is changed to 100, the maximum output offset voltage will be 8.5mV, which is the worst case.
The test of input offset voltage is introduced in "Detailed explanation and analysis of op amp parameters - part 2, how to measure input bias current Ib, offset current Ios". If you are interested, you can take a look. There is also a simple test method, as shown below:
Vos = Vout/1001
It should be noted that when using the simple method to test the input offset voltage of a single-power op amp, it is necessary to short-circuit the input and provide a low-noise stable voltage bias. See the figure below.
The following are some low temperature drift op amps, their maximum drift is only 0.05uV/℃. The maximum input offset voltage Vio is only 5uV.
4. Quick calculation of op amp noise
This article is not about the noise theory of op amps. Art Kay, a senior application manager at TI, has written a series of articles to analyze the noise of op amps. I believe most analog circuit engineers have read them. Some engineers in China have even translated them into Chinese.
Today, we will mainly analyze the noise composition of op amp circuits from a top-down perspective, and discuss several key points and complicated parts when calculating. Most importantly, we will provide you with a convenient calculation tool that is easy to use and makes noise calculation simple.
In the reverse amplifier circuit composed of the operational amplifier, the noise mainly comes from three aspects:
( 1) Input noise voltage en of the op amp (data and curves are available in the datasheet)
( 2) The input current noise in of the op amp (data and curves can also be found in the datasheet). This needs to flow through a resistor and then be converted into voltage noise.
( 3) The thermal noise of resistors R1 and Rf that set the gain can be calculated using the classic formula: Noise =√(4kTKRΔf). This is unavoidable. In many cases, it will become the main source of noise.
The calculation of the op amp noise is to find out these three values one by one. Since these noises are unrelated, their vector sum is the total input noise of the op amp. Multiplying it by the noise gain gives the output noise, as shown below. It seems simple, but it is actually very troublesome.
We add the calculated total input noise to the positive input of the ideal op amp to get the noise model of the op amp. Note that it is the positive input, so the gain of the noise for both the unidirectional amplifier circuit and the reverse amplifier circuit is G=1+Rf/R1. We can simply understand that the noise is a signal superimposed on the op amp input. As shown in the figure below
An important issue was mentioned above, the noise gain of the op amp. Another important issue is the noise bandwidth of the op amp. The op amp noise parameters given in the datasheet are generally spectral density values such as 1.1nV√Hz. In other words, it is necessary to integrate it in the noise bandwidth to get the RMS voltage value of the noise. The noise bandwidth is different from the -3dB bandwidth of the signal. To be precise, it is the bandwidth of the Brickwall filter. Simply put, it is to convert the actual filter response curve into the bandwidth of the ideal low-pass filter while ensuring that the included area remains unchanged. Fortunately, we can look up the table to get the conversion coefficient between the -3dB bandwidth of the N-order filter and the bandwidth of the Brickwall filter. As shown in the following table
It looks troublesome, but don't worry, there are more troublesome things, that is, the input voltage noise and input current noise of the op amp are related to the frequency. At very low frequencies (0.1Hz-10Hz), it is mainly 1/f noise, and later it is mainly white noise, as shown in the following figure.
It needs to be segmented.
The following figure shows the calculation of noise voltage. As long as the value of 1/f noise at a specific frequency and the value of flat noise are input, the noise density at different frequencies can be calculated. By inputting the start and end frequencies of the frequency band, the contribution rate of each noise in this frequency band can be analyzed.
The figure below shows the method for calculating the noise density of the same-direction amplifier circuit (taking OPA627 as an example). You only need to input the signal source resistance, op amp voltage noise, op amp current noise, resistance value and temperature to calculate the noise density of the output circuit, which greatly improves the calculation efficiency. The calculation results also give the contribution rate of each noise source, which is convenient for us to optimize the noise design.
5. Power Supply Rejection Ratio DC-PSRR
This section discusses the power supply rejection ratio of op amps. In an ideal op amp, the characteristics of the op amp will not change with changes in the power supply voltage. Of course, when analyzing an ideal op amp, the power supply we use will also be assumed to be an ideal power supply. But the actual situation is not the case. For actual op amps, when the power supply voltage changes, it will always cause changes in the op amp parameters. This leads to an important parameter of the op amp, the power supply rejection ratio PSRR of the op amp. Wikipedia gives a detailed definition of PSRR, which is that when the power supply voltage of the op amp changes, it will cause a change in the input offset voltage of the op amp (offset voltage again). The ratio of these two changes is the PSRR of the op amp. As shown below
Usually expressed in dB. PSRR = 20log(⊿Vcc/⊿Vios). In some data sheets, it is also expressed as the ratio of offset voltage to power supply change. The unit is generally uV/V. As shown in the figure below, it is expressed in the datasheet of OPA365, which is not difficult to understand. We don't have to be sad because we can't find the ratio dB value defined in the above formula. Both of these expressions can make us clearly understand the op amp's ability to suppress power supply voltage changes.
The reason why PSSR is a finite value is also due to the incomplete matching of the differential input tubes of the op amp. The following focuses on its impact. The following figure is a calculation example of the OPA376 op amp. When the power supply voltage changes by 500mV, it will cause a change of 10uV in the input offset voltage. If the amplification factor is 2, the output end will change by 20uV. Some circuits have a larger amplification factor, and the output offset voltage changes are larger. This is enough to cause an error in a signal sent to a 16-bit ADC. (One LSB of a 16-bit ADC corresponds to a change of 15ppm of FSR).
6. Power Supply Rejection Ratio AC-PSRR
The above section discusses the DC power supply rejection ratio. In actual application circuits, the power supply voltage of the op amp may remain unchanged.
Next, we will analyze another key parameter, the op amp AC power supply rejection ratio ( AC-PSRR). This parameter is relatively more valuable in actual application circuits, but it is often overlooked. The op amp datasheet parameter table often gives the DC PSRR. The AC-PSRR is often given in the form of a graph, and we often ignore the information in the graph. However, what we ignore is often the key. The figure below is a PSRR graph in the OPA376 datasheet. From the graph, we can see two pieces of information: (1) PSRR decreases as the power supply AC frequency increases, and (2) the AC-PSRR of the positive and negative power supplies are different.
The above two points will cause unpleasant problems in the application circuit. The figure below shows that a ripple with a peak-to-peak value of 100mV and a frequency of 20kHz on the power supply will add a 20uV, 20kHz noise signal to the output of the amplifier circuit.
Usually, a linear power supply is used in the application circuit of the op amp to power the op amp and filter the power supply of the op amp. However, in order to improve efficiency and reduce power consumption, some handheld devices have to use a switching power supply to power the op amp. The frequency of the switching power supply often exceeds 100kHz, even to the MHz level. At this frequency point, the PSR capability of the op amp drops very quickly. For example, at 100kHz, the PSRR of the OPA376 is only 50dB. It is far from the DC-PSRR of more than 100dB. Another problem is that in single-power hand-held devices, the "buck-boost" of the switching capacitor is often used to convert the positive power supply into a negative power supply. After seeing the AC-PSRR of the op amp to the negative power supply in the figure above, we will sweat a little. The PSRR of the op amp refers to the change in the input offset voltage caused by the change in the power supply voltage. Therefore, the PSRR can be measured by referring to the method of measuring the offset voltage. Change the power supply voltage by ⊿Vcc, and then measure and calculate ⊿Vios to calculate the PSRR.
As mentioned above, when the op amp is powered by a switching power supply, the PSRR decreases as the frequency increases, which causes a large ripple noise at the output of the op amp. The following is a simple method, which is only suitable for low-power op amps. Add a small resistor between the DC-DC output power supply and the power source of the op amp (as shown below). If the power consumption of the op amp is less than 5mA, the voltage drop generated by this 10-ohm resistor is less than 50mV.
Let's take a look at the effect of this circuit as shown in the figure below. At 100kHz, the frequency response is -36dB, which is equivalent to adding 36dB PSRR to the op amp. This power loss is worth it in exchange for this effect.
Another effective method is to use a through-core capacitor to filter the power supply. A through-core capacitor is a three-terminal capacitor, but compared with an ordinary three-terminal capacitor, it is directly mounted on a metal panel, so its ground inductance is smaller and there is almost no influence of lead inductance. In addition, its input and output terminals are isolated by metal plates, eliminating high-frequency coupling. These two characteristics determine that the through-core capacitor has a filtering effect close to that of an ideal capacitor. For more information about the through-core capacitor, you can refer to the relevant information.
7. Common Mode Rejection Ratio CMRR
The common mode rejection ratio of an op amp is an op amp parameter that is often concerned, especially in differential amplifiers and instrumentation amplifiers. However, this section only discusses the common mode rejection ratio of op amps and the error caused by CMRR to op amps. Differential amplifiers and instrumentation amplifiers will be discussed in another article later.
Before discussing the common-mode rejection ratio of op amps, let's first understand the common-mode input voltage of op amps. The common-mode input voltage of op amps refers to the average value of the voltages of the two input pins of the op amp. Note that it is the "average value", which is very important, as shown in the figure below. For bipolar input stage op amps, the common-mode input voltage of the op amp generally cannot reach the power rail. However, the common-mode voltage of some rail to rail input op amps can reach the power rail.
In an ideal op amp, the differential mode gain of the op amp is infinite, and the common mode gain is 0. Ideals are always beautiful, but reality is always cruel. Therefore, the actual op amp is not like this. The differential mode gain of the actual op amp will not be infinite, and the common mode gain will not be zero. We define the common mode rejection ratio (CMRR) of the op amp, the ratio of the differential mode gain to the common mode gain, as follows
There is another very common parameter, which is CMR, which is actually the logarithmic representation of CMRR, as shown below:
However, these two parameters are often used interchangeably. We only need to understand that they both represent the op amp's ability to suppress common-mode signals.
The reason why the op amp can amplify the common-mode signal is, of course, something we don’t expect, but it is also inevitable. It mainly comes from the following reasons:
( 1) Mismatch of the op amp input stage. This can be divided into the following reasons:
1) Mismatch of source or drain resistance,
2) Signal source resistance
3) Junction capacitance between gate and drain
4) Mismatch of forward transconductance
5) Gate leakage current
( 2) Output impedance of the tail current source
( 3) The parasitic capacitance of the tail current source changes with the frequency.
Let's take a look at some of the reasons above and see their impact:
(1) Resistor mismatch. As shown in the figure below, due to resistor mismatch, a common-mode voltage change ΔVin will be converted into a differential-mode voltage at points X and Y.
The calculation is as follows: the differential mode signal introduced by the mismatch resistance ΔRd will be converted into noise of the differential stage output signal.
(2) The mismatch of the input transistors will cause a slight difference in the current of the two transistors, and the transconductance of the two is different.
Due to the mismatch of the input stage tubes, the common-mode signal will be converted into a differential-mode error, which can be expressed by the following formula, which represents the CMRR caused by the mismatched transconductance .
(3) Another reason is that the parasitic capacitance of the tailing constant current source will change with frequency. This will cause the current of this constant current source to change. The purpose of replacing the emitter or source resistor of the differential input with a constant current source is to keep the current constant and high impedance. However, if its current changes with frequency, it will inevitably reduce the common-mode rejection capability of the differential input.
8. Impact of Common Mode Rejection Ratio CMRR
The previous section briefly introduced the definition of common mode rejection ratio and the causes of it. The following will introduce its impact. The purpose of this series of posts is to clarify the definition of op amp parameters, analyze the causes of this problem, explain the impact of this parameter on the circuit, and finally try to introduce some empirical methods to minimize and avoid these effects.
Simply put, CMRR is a DC accuracy parameter of the op amp. The quality of CMRR will affect the output error of the op amp's amplification circuit.
The following table shows the CMRR in the OPA177 datasheet. Note that the values in the table refer to the DC CMRR within the input common-mode voltage range. Its minimum value is 130dB, which is a very high value.
Since CMRR is a finite value, when there is a common-mode voltage Vcm at the op amp input, it will introduce an input offset voltage, which we call Vos_CMRR. As shown in the figure below
When the common mode voltage is 5V, the offset voltage is 1.58uV. The calculation process is as follows, and the DC common mode rejection ratio is converted into a ratio:
For the circuit with G=2 in the figure above , the output error is 3.16uV. For a 24-bit ADC with a reference source of 2.5V and bipolar input, this is equivalent to causing a DC error of 11 LSBs, which directly affects the accuracy of the last four bits.
Here is another bad effect. The CMRR of the op amp decreases as the frequency increases. The datasheet usually gives a curve graph to show this change. As shown in the figure below, this is a very unpleasant feature.
We can calculate the impact of this characteristic, as shown in the figure below. When the common mode signal is a 20Vpp@1KHz sinusoidal signal, the input error voltage it introduces will be Vos_CMRR_AC=200uV@1kHz. For the amplifier circuit with Gain=2, its input error signal will be 400uV@1kHz.
One thing needs to be noted, for the reverse proportional amplifier circuit, as shown in the figure below, its same direction end is connected to the ground, due to the "virtual short", the common mode signal of this op amp will be 0, and will not change with the change of the signal. Therefore, the error caused by the common mode signal is very small.
As for the same-direction proportional amplifier circuit, as shown in the figure below, its same-direction terminal is connected to the signal, due to the "virtual short". The common-mode voltage of this op amp is the voltage of the signal. If the signal itself is a very high frequency signal with a large amplitude, then the Vos_CMRR_AC introduced by this signal will definitely be very large. At this time, an op amp with a still very high CMRR at the signal frequency should be selected. After the above analysis, even so, the impact of Vos_CMRR_AC may be very serious.
Finally, let me briefly introduce the CMRR test of the op amp . Usually people think of the method shown in the figure below to test CMRR. This method seems simple, but there is a big problem, that is, it requires a very high resistance matching. In order to test the op amp with CMRR>100dB, a resistance below 1ppm is required. This is almost impractical.
The simple and easy way is the one shown in the figure below. It requires much lower matching degree of resistors.
Assume that the output voltage of the signal source is VS, and the measured output voltage of the auxiliary amplifier is VL0, then we have
9. DC error of amplifier circuit
The previous section analyzed the main DC parameters of the op amp in detail. The reason we analyze them is that they will introduce DC errors into our circuits. The main purpose of this post is to find out the reasons that affect the DC error of the op amp and explain how it affects it. So that engineers can pay more attention when designing precision amplifier circuits.
First, let's take a look at the theoretical model of the same amplifier circuit, as shown below
This circuit is very common in the application circuits of op amps. Its output is eo. It is equal to the closed-loop gain (1/β) multiplied by the input signal. Here, we need to pay more attention to the input signal, which is composed of the circuit input signal ei minus the error eid introduced by the op amp. In the formula, β is the feedback coefficient. For a typical unidirectional amplifier circuit like the one shown below, its value is R1/(R1+R2). This is described in detail in analog electronics textbooks, so I won’t go into details. This article will focus more on eid.
For EID, our first reaction may be the input offset voltage, and the further reaction is the error voltage caused by the input bias current flowing through the resistor network. But in fact, there are far more than these two factors, and they have many other factors. Then let's show its true face:
There are quite a lot of terms on the right side of the equation above. We are not disappointed. So many parameters are involved in making DC errors. Of course, these parameters are the ones mentioned in part 1 to part 8.
10. Factors affecting DC error in amplifier circuits
Let's take a closer look at the formula mentioned in the previous section:
Let’s look at them one by one.
( 1) Vos, input offset voltage, is well known to everyone, so I won’t go into details. The worse thing about it is that it is not a constant value, it will drift with temperature.
( 2) Ib+, the input bias current at the same direction end, flows through the equivalent impedance of the same direction end to form an error voltage.
( 3) Ib-, reverse end input bias current, which flows through the reverse end equivalent impedance to form an error voltage.
Some people may have noticed how to calculate the input impedance. The following figure will make it clear. In short, the input resistance (signal source resistance plus input resistance) is connected in parallel with the feedback resistance. Don't forget the signal source resistance, because we often use high impedance sensors as signal sources.
( 4) en, equivalent input noise. I understand this value to be more than the en given in the datasheet, such as 1.1nV√Hz. It integrates the contributions of voltage noise, current noise, and resistor noise. It is the value of all noise equivalent to the input. For details, please refer to Art Kay's article and part 4 of this series of blog posts.
( 5) eo/A, this expression may have never been paid attention to by many people. The reason for this term is that the open-loop gain A of the op amp is not 0. This is because the equivalent input error is different due to the different input values. For example, if the output value is 5V, the open-loop gain is 100dB, which is not low. The error converted to the input end is 50uV, which is not a small number.
( 6) eicm/CMRR, needless to say, it is the common-mode voltage at the input divided by the common-mode rejection ratio. There is another disadvantage, the CMRR of the op amp decreases with the increase of the common-mode signal frequency. When the common-mode signal reaches above 10KHz, the CMRR of many op amps drops by dozens of dB compared to DC.
( 7) ΔVs/PSRR, the error introduced by the variation of the power supply voltage. Similarly, the AC PSRR decreases with increasing frequency.
After reading this, you may think that this small error is just a drop in the bucket, at most at the mV level, or even at the uV level. Don't forget that it has to be multiplied by a gain. If the input error is 100uV, and the gain is 100 times, the output error signal is 10mV.
Input_error x Gain = Output Error
If you still think it's nothing, here's another empirical value: one LSB of a 16-bit ADC with a full scale of 5V is about 75uV. An error of just 75uV will cause a change in one bit of the ADC. If the output error signal of the amplifier circuit is 1mV, this signal will directly cause an error of more than 13 LSBs to the ADC.
This output error is a mixed bag. There is a DC component, which can be removed by ADC sampling and correction. There is a noise signal and an AC component. The most unexpected thing is that it will drift with temperature.
When designing circuits, we can use the above analysis to find out the main factors that cause DC errors, and then work hard to reduce them.
11. Input impedance and input capacitance
The following figure illustrates the input impedance characteristics of the op amp. There are two main parameters, input impedance and input capacitance. For voltage feedback op amps, the input impedance is mainly determined by the input stage, generally BJT input stage op amps. The common mode input impedance will be greater than 40MΩ. The differential mode input impedance is greater than 200GΩ. For JFET and CMOS input stage op amps, the input impedance is much larger. This impedance usually behaves as a resistor. It is known to us as common sense.
What deserves more attention is the input capacitance of the op amp. This parameter is usually listed in the table of the datasheet, but it is often overlooked. The input capacitance of the op amp is usually divided into common mode input capacitance Ccm and differential mode input capacitance Cdiff. The following is the input capacitance listed in the datasheet of OPA376.
For op amps with EMI suppression features, such as the LMV832, its input capacitance will be designed to be larger. Below is the input capacitance value of the LMV832 with EMI suppression function.
The input common mode capacitance Ccm and differential mode capacitance Cdiff of the op amp will form the input capacitance Cin of the op amp. In many applications, the input capacitance of the operational amplifier will not cause any problem. However, in some applications, it will cause instability of the amplifier circuit. In particular, the capacitance at the reverse input is one of the major culprits of instability in the amplifier circuit. The following figure shows the model of the op amp under the influence of input capacitance.
The capacitor at the inverting input introduces a pole in the loop gain of the op amp. It is this pole that may cause instability in the amplifier circuit under certain conditions.
The pole introduced by the op amp input capacitor is as follows. Even if this pole is within the 0-dB crossover frequency, but very close to the 0-dB crossover frequency, it may cause problems. At the frequency point of this pole, the phase will have a 45-degree phase delay, which is likely to reduce the phase margin of the amplifier circuit. For example, the 0-dB crossover frequency of the amplifier circuit is 2MHz. The phase margin at 2MHz is 89°. If the frequency point of this pole is also at 2MHz, it will reduce the phase margin by 45°. It becomes φ = 89° – 45° = 44°. The phase margin of 44 degrees is not enough.
Usually the input capacitance of the amplifier circuit is composed not only of the input capacitance of the op amp, but also of the stray capacitance caused by the wiring and the pin capacitance. External stray capacitance at the inverting input of the operational amplifier should be avoided as much as possible, especially in high-speed applications. The ground plane should be removed from the area around the inverting input to minimize the PC board stray capacitance. In addition, all connections to this pin should be as short as possible.
In some applications, feedback capacitors are often added to increase the stability of the amplifier circuit. The loop gain of the circuit after adding the feedback capacitor is . It can be seen that the feedback compensation capacitor introduces a zero point into the loop gain.
12. Measurement of input capacitance Cin
Normally we can get the op amp input capacitance Ccm and Cdif from the op amp datasheet. These values are usually typical values. In some cases, it may be necessary to actually measure the op amp input capacitance. Here is a practical test method.
The figure below is the test schematic. The basic test principle is to connect the op amp as a follower, and then connect a resistor in series at the same-direction input end (the resistance is generally between 100K-1M). This resistor and the input capacitance of the op amp will form an RC circuit. We test the -3dB frequency of this circuit. If the series resistance is known, the input capacitance of the op amp can be calculated. It should be noted here that the resistor also has an equivalent parallel capacitance. For example, the equivalent parallel capacitance of a typical 1/4W capacitor is about 0.3pF. We can reduce the equivalent parallel capacitance of the resistor by connecting a series resistor.
The picture below is the actual test setup. The instruments used are network analyzer, high impedance FET probe, and power separator. Why not use an oscilloscope? There is a reason for this.
Since the input capacitance of an op amp is usually less than 10pF, the capacitance of an oscilloscope probe is usually around 10pF. If you use an oscilloscope probe to measure the input capacitance of an op amp, you will not be able to measure it accurately. Therefore, you need to use a high impedance FET probe with a capacitance less than 1pF, such as the Tektronix P6245.
Here is a brief description of the test method:
( 1) First, we need to test the stray capacitance of the PCB when the op amp is not installed. The test result of the network analyzer reads the -3d frequency point f1. And calculate the stray capacitance:
( 2) Install an op amp in the circuit, and then use a network analyzer to test the -3dB frequency point f2. And calculate the sum of the op amp input capacitance and stray capacitance:
( 3) If the series resistance we choose is much smaller than the common-mode resistance of the op amp, then we can regard Rth1=Rth2. Then the above formula can be written as:
In this way, by finding the difference, the input capacitance of the op amp can be calculated.
13. Rail to rail input
With the widespread use of single-supply op amps, rail-to-rail input has become a fashionable term. Most low-voltage single-supply op amps now have rail-to-rail input.
Let me say a few words to explain rail-to-rail. The rail here refers to the power rail. The two power supply voltages of the op amp are +/-15V. These two power supply voltages limit the input and output signals of the op amp just like two parallel "rails" with a distance of 30V. The rail-to-rail input of the op amp means that the input signal voltage of the op amp can reach the two rails of the power supply and remain undistorted. For example, the input signal voltage can reach +/-15V in the above example. The input voltage range of the op amp can be found in the datasheet of the op amp. It is the common-mode voltage range Vcm (Common-Mode Voltage Range). The following table shows the input voltage range of OPA365, which shows that it is a typical rail-to-rail input op amp.
General BJT and JFET are non-rail-to-rail input op amps. As shown in the following table, the common-mode input voltage range of OPA827 is (V-) +3V to (V+) -3V, which is a typical non-rail-to-rail op amp.
There are usually three structures for the input stage of a single-power (let's call it "single-power") op amp. The first is to use PMOS as a differential input stage. The voltage of such an op amp input stage can be 0.2 or even 0.3V lower than the negative power rail, but cannot reach the positive power rail, such as OPA336. The following table shows the input voltage range of OPA336 as marked in the datasheet.
Its input stage principle block diagram is shown below, a typical PMOS differential input stage.
Since the input voltage of the PMOS differential input stage cannot reach the positive power rail, what about NMOS? That's right. The input voltage of the NMOS differential input stage can reach the positive power rail, but cannot reach the negative power rail, and is generally above 1.2V of the negative power rail.
At this time, someone thought of connecting the PMOS and NMOS differential input stages in parallel. When the PMOS differential input stage is close to the negative power rail, the NMOS differential input stage is working, and when the NMOS differential input stage is close to the positive power rail, the rail-to-rail input of the op amp can be realized in this way. It's so clever. Indeed, the early rail-to-rail input op amps were designed in this way. And this technology is also widely used now. The following figure shows the input stage of OPA703, which is a typical op amp input stage with PMOS and NMOS connected in parallel. When the input common-mode voltage is (Vss-)-0.3V<vcm<(vss+)-2v, pmos is in working state and nmos is in off state. When the input common-mode voltage is (vss-)-2v<vcm<(vss+)+0.3v, nmos is in working state and pmos is in off state.
</vcm<(vss+)-2v, pmos is in working state and nmos is in off state. When the input common mode voltage is (vss-)-2v<vcm<(vss+)+0.3v, nmos is in working state and pmos is in off state.
The following table shows the common-mode voltage input range (V-) -0.3V to (V+) +0.3V given in the OPA703 datasheet.
The bipolar input stage also has such a structure. The following figure shows a differential input stage formed by connecting a typical PNP and NPN transistor in parallel.
14. Rail-to-rail input
13 mentioned that the commonly used rail-to-rail op amp uses the method of connecting NMOS and PMOS differential input stages in parallel. This method cleverly solves the problem that the input signal cannot reach the two power rails. It is widely used in rail-to-rail input op amps today.
However, this type of parallel differential input stage op amp has an inherent problem, which is the input offset voltage crossover problem. As shown in the figure below, this is the input front stage of the parallel differential input structure op amp.
The figure below shows the input offset voltage of this op amp. As the common-mode voltage increases, the PMOS will be turned off at around 2V (the value used for example), and the NMOS will be turned on at this critical juncture. The input offset voltage of the op amp changes. This is understandable. The input offset voltages of the two sets of input stages with different structures are different. When the baton is handed over, this offset voltage also completes the handover. For DC signals, this problem will cause a sudden change in error. For sinusoidal AC signals, this problem will cause signal distortion. A small step is introduced at the crossover point.
To solve this problem, two leading differential input stages are designed. The first structure is shown in the figure below. The PMOS differential input stage can reach the negative power rail, but cannot reach the positive power rail, which is always about 1V away. We increase the power supply of the input stage by 1.8V internally. As the tide rises, so do all boats. Such an input stage can reach the positive power rail of the op amp. Since there is only one set of differential input stages, there will be no problem of input offset voltage crossover.
This technology is applied to TI's single-power op amp OPAl365, as shown below.
This is not the end. Another technology is used in TI's single-supply rail-to-rail op amp. This is the self-zeroing technology. The following figure shows the self-zeroing technology (MOSFET Zero Drift) before and after. The input offset voltage jump is very small.
This technology is applied in TI's OPA333 op amp. The following table shows the Vcm input voltage range of OPA333.
15. Open loop gain Aol
The open-loop gain Aol of an ideal op amp is infinite. This is a basic knowledge of op amps that we learned in analog electronics textbooks. But the reality is always cruel, so cruel that the open-loop gain of all op amps is not infinite, but a finite value. This limitation will cause a problem. Another issue to be discussed in this article is the gain-bandwidth product. In fact, I would like to talk more about the gain-bandwidth curve.
In the absence of negative feedback (open loop), the gain of the operational amplifier is called open loop gain, or AOL for short. This sentence simply defines the open loop gain of the operational amplifier. The actual open loop gain of the operational amplifier can be high or low, and it will change with temperature, which is something we don't want to see.
Let's first talk about the adverse effects of open-loop gain. The disadvantage of a finite open-loop gain is not only that op amps are not ideal. It also brings about a problem that is often overlooked - error.
The following figure shows the parameters of open-loop gain given in the datasheet of OPAl369. The first thing that comes into view is that the most typical value of open-loop gain is 134dB, and the minimum value is 114dB. This shows that for a large number of op amps of the same model, their respective open-loop gains are distributed to a certain extent.
The second thing that comes into view is that the open loop gain of the op amp varies with temperature. Of course, it gets worse. The minimum value in the entire op amp's operating range may reach 90dB.
Next, we calculate the effect of Aol on the amplifier circuit. The following figure is a common in-phase proportional amplifier circuit.
If Aol is taken into account, its voltage gain is
When Avol is assumed to be infinite, the gain of the above amplifier circuit is simplified to
The above is what is covered in the analog electronics textbook. But if we are serious about calculating the effect of Avol, when Avol is a typical value of 134dB, the gain of the above circuit is:
The error is:
This result is not bad, equivalent to an error of 20ppm.
If applied over a wide temperature range, in the worst case, when Avol is the minimum value of 90dB over temperature, the gain error is as follows.
Oah, megadon. 3 parts per thousand error, for a 16-bit ADC, this is equivalent to 200 codes. It's really a lot.
Therefore, we can draw the following conclusions about Aol:
(1) It cannot be taken lightly, as it does affect the DC error of the op amp, as mentioned in the previous part.
(2) It varies with temperature, and in the worst case, the error it introduces can be quite significant.
(3) Op amps with low open-loop gain are not suitable for high-precision amplification.
As Bruce wrote in his blog, Aol and offset are cousins. Viewing the finite open loop gain as an offset voltage that changes with the output voltage provides an intuitive way to estimate the error. If the DC open loop gain is 100dB, this is equivalent to 1/10^(100dB/20) = 10uV/V. Therefore, for the output to swing 1 volt, the input voltage must change 10uV. Think of it as an offset voltage that changes with the DC output voltage. For an output swing of 9 volts, the change is 90uV. Maybe this change is insignificant for your circuit, or maybe it is.
16. Gain Bandwidth Product (GBW)
Everyone is familiar with the gain-bandwidth product of op amps. It was one of the few parameters that I remember clearly when I first learned about op amps in college.
I still want to write a post to dig deeper into this parameter (Uncle Zhao's sketch "Digging at the Ancestor's Grave"). For a single-pole response, the open-loop gain decreases at 6 dB/octave. That is, if we double the frequency, the gain will decrease by a factor of two. Conversely, if the frequency is halved, the open-loop gain will double, resulting in the so-called gain-bandwidth product. The following table shows the typical value of the gain-bandwidth product of 5.5MHz given in the datasheet of the op amp OPA376.
More useful than the parameters in this table is the open-loop gain curve of the op amp. The following figure is the open-loop gain curve given in the datasheet of the OPA376.
The unit gain bandwidth of an op amp is also often seen in some materials. It refers to the -3dB bandwidth when the gain of the op amp is 1 (it is marked in the figure above). It is numerically equal to the gain bandwidth product of the op amp, although the names are different. Let's dig deeper into the curve in the figure. First, observe the gain curve. It has an inflection point around 1Hz. After this inflection point, the open-loop gain of the op amp begins to decrease at -6dB/2 octave (or -20dB/decade). It is because of this inflection point that the op amp has a gain bandwidth. This is different from the infinite open-loop gain in an ideal op amp.
The value of the gain bandwidth product has an implicit condition, that is, this value is the bandwidth under small signals. How small is this often-mentioned small signal? I remember it is 100mVpp. But our op amps are often used to amplify large signals, and the output is around a few volts. A common problem for engineers is that the calculated bandwidth is enough, but why is it not enough in the actual circuit? This is the reason. Therefore, the large signal bandwidth also needs to pay attention to a parameter, the slew rate SR. It will be introduced in future posts.
In summary, the gain-bandwidth product represents the gain-bandwidth of small signals. Large signals are another matter.
17. Talking about operational amplifier stability from the open-loop gain curve
Let's start with the open-loop gain curve in part 16. Why does the open-loop gain curve have an inflection point at low frequencies? This inflection point is the main pole of the op amp. There are also multiple poles or zeros in the circuit inside the op amp. This point is the main pole of the circuit inside the op amp (whether it is three-stage or two-stage). If it is a three-stage op amp, this pole is generally set by the Miller capacitor of the second stage. The figure below is the schematic diagram of a single-pole op amp.
In the figure, Cc is the capacitor that sets the dominant pole. The figure below is a schematic diagram of the internal circuit of a two-stage fully differential op amp. Look for Cc in the figure. It is on the M5 tube and is amplified according to the Miller effect.
Why do we need to quote Cc to set the main pole of the op amp, instead of designing the op amp to have a constant open-loop gain such as 130dB, which would be closer to the ideal op amp? The main reason is that the introduction of this main pole compensation can ensure the stability of the op amp. And for stability, the design engineer will try to lower the main pole. The earliest pioneer op amps such as uA709 did not have internal compensation, so external compensation was required, otherwise it would easily cause oscillation.
Of course, this pole will introduce a 90-degree phase shift. Let's look at the phase curve in the figure above. There is another 45-degree phase shift near 10MHz. This can only be explained by one condition, that is, there is another pole near this point, but this pole is already outside the unity gain band, so it will not cause oscillation. But it will also introduce a problem, making the phase margin of the op amp lower. Looking at the figure again, we find that at 5.5MHz, the phase shift seems to be not just 90 degrees, but about 110 degrees. This makes the phase margin of the op amp about 70 degrees.
If we dig deeper, we will find that when analyzing the stability of an op amp, we will always analyze the loop gain Aβ of the op amp. We will always hear that when Aβ=-1, the op amp will always oscillate. That is, the phase shift in the loop reaches 180 degrees. A is the open-loop gain, and β is the feedback coefficient of the amplifier circuit. The following figure simply illustrates the feedback network and β of the op amp.
Basically, there are two poles in the loop. Unfortunately, there is already a pole in A in the op amp, which introduces a 90 degree (or even more) phase shift. It is not difficult to introduce another 90 degree phase shift. Of course, this is not what we want to see.
The loop gain Aβ can be written as A divided by the inverse of the feedback factor, 1/β, which is actually the closed-loop gain of the circuit:
The above formula is still difficult to analyze, so if we write it in logarithmic form, it will be very useful to us.
What does this formula represent on the Bode diagram? See the figure below.
Hmm, looks familiar! Yes, this picture comes from a series of articles written by senior engineer Tim Green on op amp stability. The area with double arrows in the picture is the loop gain of the amplifier circuit. As mentioned above, if there are two poles in the loop gain, oscillation will occur. What is the manifestation of this in the Bode diagram above? It is that the merging speed of the op amp open loop gain A and the inverse of the feedback coefficient 1/β when they intersect in the Bode diagram is greater than or equal to 40dB/decade (in the above figure, there is only the main pole of the op amp, so the merging speed is 20dB/decade).
What causes two poles in the loop gain? From Aβ, we can see that A already has one pole. If A adds another pole, or β introduces another pole, it will be enough to make the circuit unstable. This is just a starting point.
18. Slew rate (SR)
I always think that the slew rate (SR) of an op amp is as important as its gain bandwidth product GBW. But it is often overlooked. The reason why it is important is that the gain bandwidth product GBW is tested under small signal conditions. The signals processed by the op amp are often very large amplitude signals, which requires more attention to the slew rate of the op amp.
The slew rate can be understood as the maximum change speed of the op amp output signal when a step signal is input to the op amp, as shown in the figure below.
Its mathematical expression is:
Therefore, the unit of slew rate found in the op amp data sheet is V/us. The following table is the slew rate of the op amp marked in the op amp datasheet.
I have measured the waveform of OPA333's response to a step signal in the lab, as shown below. I hope it will be more intuitive for everyone:
After discussing the definition and phenomenon, let's look at the source of the slew rate SR. First, let's look at the internal structure of the op amp:
This diagram looks familiar. Yes, the SR of the op amp is mainly limited by the internal second-stage Cc capacitor. This capacitor also determines the bandwidth of the op amp. The slew rate of the op amp is mainly determined by the speed of charging the second-stage Miller capacitor. If you look deeper, the size of this capacitor will affect the slew rate of the op amp, and the size of the charging current will also affect the charging speed. This also explains why the slew rate of general ultra-low power op amps is not too high. It's like a slow water flow and a large pool. It will take longer to fill the pool.
The following table shows the slew rate and quiescent current of some commonly used TI op amps:
The above briefly talked about a factor that affects the slew rate SR. Now let's talk about the impact of SR on the amplifier circuit. Its direct impact is to make the rise time or fall time of the output signal too slow, thus causing distortion. The figure below is the waveform of the OPA333 when the gain G=10 is tested. Since the gain-bandwidth product of OPA333 is 350kHz, the bandwidth is theoretically 35kHz when the gain is 10. But the figure below is the result of the test at 24kHz. Obviously, the output waveform has been distorted because the slew rate is not enough. The bandwidth has also become about 27kHz.
19. Full Power Bandwidth (FPBW)
Therefore, an important parameter is introduced here, which is as important as the gain-bandwidth product. That is the full power bandwidth of the op amp. Although it is just a mathematical derivation.
For a sinusoidal output signal, the output voltage can be expressed as:
Vout = Vp * sin(2*pi*f*t)
The output voltage is differentiated with respect to time:
The max in the above formula refers to the maximum value of the cosine signal after derivation at t = 0. This is easy to understand, that is, the slew rate of the original sine signal is the largest at t = 0.
It can be seen that the slew rate represented by dV/dt is related to the frequency sequence of the signal and the output amplitude of the signal. In the above formula, if Vp is the full amplitude of the output of the op amp. Then the above formula can be expressed as
At this time, FPBW is the full power bandwidth of the op amp. Remember it, it is very important. For example, if you want to get a 10Vo-p amplitude of a sine wave within 100Khz, according to the formula, the conversion rate needs to be above 6.3v/us. It can be seen that the full power bandwidth is determined by the slew rate and the amplitude of the output signal. That is, when the slew rate is constant, the larger the amplitude of the output signal, the smaller the full power bandwidth. This also explains the test results of OPA333 above.
Here we need to talk about an important formula, which is the relationship between the rise time and bandwidth of the op amp. It is as follows. It looks familiar. This formula has been seen in many places. It is too important, so remember it.
Today we will analyze the origin of this formula in more depth. In fact, it is calculated from the response of a first-order system. The frequency response of a first-order RC is
The step response of a first-order system is given by the following equation.
When Vo=0.1Vm, t=0.1RC. (-ln0.9 =0.1) When Vo=0.9Vm, t=2.3RC (-ln0.1=2.3). Then the time of RC step response is Tr=2.2RC.
The bandwidth of a first-order RC can be expressed as: BW = 1/(2*pi*RC). There is also RC in the rise time, and these two RCs are the same. This sentence is nonsense. Then Tr = 2.2/(2*pi* BW) = 0.35/BW.
Next, we simulate this conclusion using TINA. The op amp is OPA2188, and the gain-bandwidth product is 2MHz. The op amp is set to a gain-1, non-inverting amplifier circuit. The input signal is a 10mV step signal. The rise time of the output signal is 220.8ns-82.5nS=138.3nS.
Let's take a look at the calculation results: The calculation result is 175nS. There is an error of about 20%. But it is also of good reference value.
20. Settling Time
I believe that not many people pay attention to the op amp settling time, but the op amp settling time is very important for the subsequent ADC. For example, for a 16-bit ADC, the voltage range corresponding to one LSB is 15ppm (15 millionths) of its full scale. If the op amp driving the ADC has not reached the final value before it is sampled by the ADC, this will inevitably cause ADC sampling errors.
The settling time of an amplifier is the time required for the output response of the op amp to enter and remain within the specified error band when the input is a step signal. Common values for this error are 0.1%, 0.05%, and 0.01%. A tragedy is that the error size is not linearly related to the settling time. For example, the settling time for an error of 0.01% may be more than 30 times the settling time for an error of 0.1%. Amazing, right? The figure below is an example of the settling time of an op amp. The settling time is the time from the start of the step signal to the time when the signal error reaches the target value. As can be seen from the figure, the response of the op amp to the step signal will be a second-order response with overshoot and ringing. This response looks familiar, like the second-order response of a control system. So the following analysis is similar to the control system.
The setup time of an op amp is mainly composed of two sections. The first section is the process of the output voltage of the op amp reaching the target value from the starting value. This process is a nonlinear process. The length of this section is determined by the current charging the compensation capacitor of the op amp. Regarding this compensation voltage, it has been mentioned in the slew rate of the op amp. Therefore, it can also be understood that the first period of time is related to the slew rate of the op amp (the determining factor of the slew rate is also the speed of charging the compensation capacitor of the op amp). The second period of time means that the output is close to the final target value. After entering this stage, the op amp is in the quasi-linear region. The characteristics of this stage are mainly affected by the zero -pole pair (doublets) of the op amp. In high-speed op amps, the slew rate of the op amp is very high, so the first period of time is very short, so the setup time is mainly determined by the second period of time.
For the second period, those interested can refer to B.Yeshwant Kamath's classic paper
Relationship Between Frequency Response and Settling Time of Operational Amplifiers
The measurement method of the settling time may require a relatively precise circuit and an instrument with good parameters. There are also classic articles introducing it on the Internet. If you are interested, you can look for it.
Measuring op amp settling time by using sample-and-hold technique
From the perspective of op amp indicators, the op amp settling time is affected by the large signal parameter - slew rate (SR) and the small signal parameter - closed-loop gain. The following figure shows the relationship between the settling time and closed-loop gain of an op amp.
It can be seen from the graph that as the closed-loop gain increases, the settling time also increases. This is because at high gain, the closed-loop bandwidth of the op amp will decrease, so the loop gain (AolB) that adjusts the output error will also decrease. This ultimately results in an increase in the settling time of the amplifier circuit.
Finally, let me say that for data sampling and holding circuits, the settling time is very important. Especially for ADC inputs that need to be switched between different signals through a multiplexer. Be sure to wait until the signal is settling before sampling. Otherwise, unpredictable errors will occur.
21. Total Harmonic Distortion (THD)
In this part, I am going to write about the total harmonic distortion of op amps. In fact, it is not just total harmonic distortion, but also harmonic distortion, total harmonic distortion and noise (THD+N), which are all important parameters for evaluating op amps in terms of harmonic distortion.
The total harmonic distortion (THD) of an op amp is the ratio of the root mean square value of each harmonic (2nd, 3rd, to nth) in the op amp input signal to the RMS value of the fundamental wave of the output signal when the op amp input signal is a pure sine wave (here, pure sine wave refers to a sine wave without harmonics). It is defined as follows:
In actual testing, only the first five harmonics ( 2nd to 6th) are usually tested. This is because the amplitude of the harmonic decreases rapidly as the harmonic order increases. Harmonics above the sixth order already account for a very small proportion of the total harmonics, and are relatively just a drizzle. Therefore, only measuring the first five harmonics is sufficient to reflect all the harmonic components. (Of course, in some manufacturers' ADCs, they will measure the 2nd to 9th harmonics, and the results will be more accurate)
The total harmonic distortion plus noise of the op amp is easy to understand. It is the denominator of the above equation plus the RMS value of the noise, which is defined as follows: Vnoise in the equation refers to the RMS value of the noise within the measurable bandwidth.
In many manufacturers' data sheets, the THD indicated actually represents THD+N. This is because most test systems do not distinguish between signal-related harmonics and other noise signals. The following table shows the THD+N values indicated in the datasheet:
Here is a brief explanation. Generally in audio systems, THD (or THD+N) is expressed in percentage, as shown in the table above. In communication systems, THD+N is expressed in dB.
The THD measurement method is generally to filter out the fundamental frequency of the input signal with a narrowband notch filter, and then test the remaining signal components (including harmonics and noise). The commonly used instrument for measuring audio THD is Audio Precision.
Next, let's talk about a chart that often appears in the datasheet of an op amp . The THD+N of an op amp is related to the closed-loop gain of the amplifier circuit. The higher the gain, the lower the TND+N. This is because when the closed-loop gain increases, the loop gain of the amplifier circuit will decrease. This reduces the op amp's ability to correct nonlinear errors. This leads to the fundamental reason for the harmonic distortion of the input, which is due to the nonlinear effects of the internal devices to a greater or lesser extent.
The values of total harmonic distortion and noise indicated in the table in the datasheet are tested in the amplifier circuit with a gain of 1. Therefore, it is a very good value, and it is no longer surprising to see that TND+N deteriorates when the amplification factor of the circuit we designed increases.
Another point is that many op amps now have rail-to-rail input and output, and the nominal signal is generally only about 10mV or even lower from the power rail of the op amp. But there is a problem. When the signal is close to the power rail, the TND+N of the signal will still deteriorate due to the response of nonlinear effects. Therefore, if you want to maintain a good TND+N, try not to make the input and output signals too close to the power rail.
22. Rail to rail output
I have been busy recently and have interrupted this topic. Now I will use the weekend to continue this topic. I hope to finish the topic of basic parameters of op amps this month and start a new topic.
Today I will use one post to write two small topics about op amp output characteristics, one is Rail-Rail output and the other is input short-circuit current.
Let's talk about rail-to-rail output first . Now, many low-voltage op amps have rail-to-rail output. The rail-to-rail output of the op amp is achieved by designing the output stage with MOS. The output stage of the early operational amplifier was an NPN emitter follower with an NPN current source or a pull-down resistor. This complementary common-emitter output stage using BJT cannot swing completely to the power rails, but can only swing within the transistor saturation voltage CESAT range of the power rails. For smaller load currents (less than 100 A), the saturation voltage may be as low as 5 to 10 mV; however, for higher load currents, the saturation voltage may increase to hundreds of millivolts.
The original meaning of rail-to-rail output is that the output voltage of the op amp can reach the power rail. But in reality, it is very close to the power rail. It is meaningless to just say such a definition. Here are some issues that need to be paid attention to about rail-to-rail output.
First look at the figure below, which is the data on the OPA376 datasheet. You can see that the output voltage from the power rail is different under different loads.
This is because an output stage built with CMOS FETs (see figure below) can provide nearly true rail-to-rail performance, but only under no-load conditions. If the op amp output must source or sink significant current, the output voltage swing is reduced by the I×R voltage drop across the FET's internal on-resistance. Generally speaking, the on-resistance of a precision amplifier is around 100 Ω, but the on-resistance of a high-current drive CMOS amplifier may be less than 10 Ω. This is the root cause of why the input cannot fully reach the power rails.
On the other hand, the voltage value of the output signal of the op amp to the rail changes with temperature. This can also be seen in the table in the datasheet of OPA376, and in the full temperature range, generally at high temperatures, the voltage value of the output signal to the rail will increase. This is because the MOS on-resistance has a positive temperature coefficient. The higher the temperature, the greater the on-resistance. This is also the reason why the voltage difference VSAT = VS – VOUT will increase in the full temperature range.
The following is a chart that is very common in op amp datasheets, but is often overlooked. It reflects an important conclusion: as the temperature rises and the output current increases, the voltage difference between the op amp output signal and the power rail VSAT = VS – VOUT also increases. The reason is as explained above. Of course, there is another problem. When the output voltage is closer to the power rail, the signal distortion will become worse. Therefore, there is no op amp that can truly reach the power rail output. According to the above reasons, it is easier to achieve high signal quality if you are farther away from the power rail.
23. Output short circuit current
The output short-circuit current of an op amp is used to indicate the ability of the op amp output stage to input or sink current. This indicator indicates the driving ability of the op amp. The maximum output short-circuit current of a general op amp is at the level of tens of mA, which does not seem to be very small. However, it can cause problems in some cases, so I will take some time to write about this issue.
The figure below shows the output short-circuit current of the OPA376. It can be seen that the source current and sink current are different, one is 30mA and the other is 50mA.
The output short-circuit current of the op amp reflects an important performance, that is, the ability to drive the load, especially when the output signal amplitude is relatively large and the load resistance is small. For example, when a 20Vpp sine wave signal is input and applied to a 100ohm, the effective value of the current applied to the load is 7.07V/100ohm=70.7mA.
Another way to determine current drive capability is to use the output current vs. output voltage graph. Figure 1 shows the output current vs. output voltage graph for the LMH6642. For most devices, there is usually one graph for both source current (Figure 2a) and sink current (Figure 2b).
Figure 2: Output characteristics of the LMH6642
Using this kind of graph, it is possible to estimate the current that an op amp can provide for a given output swing. These graphs are used by chip manufacturers to show the relationship between the output current capability of an amplifier and the output voltage.
Note that in Figure 2, "Vout from V+" is plotted against the output source current, and "Vout from V-" is plotted against the output sink current. One reason for presenting the data this way is that it can be more easily applied to single-supply or dual-supply operation than the output voltage relative to ground. Another reason is that voltage margins have a much greater effect on output current than total supply voltage, so for any supply voltage, even if the exact conditions are not found in the data sheet, this data sheet method allows the designer to make a rough calculation using a set of closest curves.
The graph can be used to predict the voltage swing for a given load. If the axes are linear, the designer only needs to add a load curve to the characteristic curve in the graph and determine the voltage swing from the intersection of the two curves.
24. Output impedance Ro and Rout
The title of this article is confusing. How can there be two output impedances for an op amp? What is the difference between them? Let's first talk about their definitions, and you can see their differences from the definitions. Ro is defined as the open-loop output impedance of the op amp. Rout is defined as the closed-loop output impedance of the op amp. The definitions seem clear, but they are still not intuitive enough to understand. Looking at the figure below, Ro is determined by the internal output stage of the op amp and does not change with the change of the closed-loop gain. It can be understood as the intrinsic parameter of the op amp.
Rout is different. It is the impedance seen from the output end after the op amp forms a closed-loop amplification circuit. It needs to be measured at the output end to be obtained. Of course, it will change with the closed-loop gain.
After talking about the definition, let's talk about the relationship between the two. The formula is very simple:
The specific derivation process is detailed in the third chapter of Tim Green's classic application document collection "Operational Amplifier Stability", so I won't repeat it here. (Two hundred words omitted here, haha).
The following analysis focuses on the impact of Ro on the amplifier circuit. Through analysis, we can see the harm of Ro and pay attention to the Ro value of the selected op amp when designing the amplifier circuit.
Because of the existence of Ro, and unlike the understanding that it is zero in the op amp, the op amp will have problems when driving a capacitive load. The main problem is that the interaction between Ro and the load capacitance introduces a pole to the loop gain of the discharge circuit. The following is the calculation result of the pole introduced by Ro and the load capacitance in the above circuit. The inflection frequency of this pole is 5.545KHz. It is very low.
fpo1 = 1/(2ПROCL)
fpo1 = 1/(2П28.7Ω1μF)
fpo1 = 5.545kHz
What happens when this pole is introduced? It makes the amplifier circuit unstable. Look at the figure below, which plots the loop gain as a Bode plot for analysis. This analysis method is described in detail in Tim Green's classic application document collection "Stability of Operational Amplifiers".
It can be seen that the introduction of this new pole Fpo1 makes the open-loop gain of the op amp roll off at a speed of 40dB/dec after Fpo1. The closing speed of the reciprocal line of its feedback coefficient at the intersection point fcl is 40dB/dec. This is enough to make the amplifier circuit unstable. (Note: The criterion for the stability of the amplifier circuit is that the closing speed of the open-loop gain Aol curve and the reciprocal curve of the feedback coefficient at the intersection point fcl is 20dB/dec, then the amplifier circuit is stable)
Even if the amplifier circuit does not oscillate, it will cause an overshoot when the amplifier circuit responds to a square wave. The following figure shows the curve of small signal overshoot under different load circuits. From the curve, it can be seen that a 500pF load circuit can cause the amplifier circuit to overshoot by 50%. This curve is very important and is given in the datasheet of many op amps.
If the value of Ro is not given in the op amp datasheet, please refer to Tim Green's application documentation collection "Operational Amplifier Stability" Part 3. The article has a detailed conversion process, so I will not attach it to save time.
25. Thermal resistance of op amp
I have been busy for a while, and today I finally took some time to finish writing a series of blogs on the detailed explanation of op amp parameters. In the last section, I will write about a very important but easily overlooked issue - the thermal resistance of the op amp.
In the datasheet of an op amp, you often see parameters such as the following table: From the datasheet of THS3091.
There are two parameters that are often seen, but are often ignored. Let's first explain what thermal resistance is. The thermal resistance of a semiconductor package refers to the temperature difference between the component and the package surface or surroundings when the device consumes 1 [W] of power. This may sound a bit difficult to understand, but look at the following figure and formula.
TJ = PD(RθJA) + TA
The formula may seem a little difficult to understand, so let's explain it bit by bit. TA refers to the ambient temperature of the chip. Tj refers to the junction temperature of the chip, which is also the temperature of the die inside the chip. The temperature difference between the two is only related to the power consumption and thermal resistance of the chip. Then, through the above formula, the definition formula of thermal resistance can be calculated:
From the above definition, we can know that the unit of thermal resistance is temperature /power consumption. This is also the unit of thermal resistance seen in the first table above.
The definition of thermal resistance is explained above. Now let's talk about two common thermal resistance parameters. The first is θJC, which indicates the thermal resistance between the junction temperature inside the chip and the chip package case. This value is generally relatively small. The other is θJA, which indicates the thermal resistance between the junction temperature of the chip and the chip ambient environment. This thermal resistance is generally larger than θJC. This is because it is more difficult for the chip case to dissipate heat to the surrounding environment. Therefore, when we touch the high-power chip case at room temperature in the laboratory, it is still very hot.
After listening to a lot of theories about the thermal resistance of op amps, look at the figure below. It is very clearly drawn and θCA is also clearly illustrated.
A lot of theories have been discussed above, and finally let me talk about some precautions for thermal design. When the operating current of the chip is very large and the thermal resistance of the chip package is relatively large, attention should be paid to the heat dissipation design. For example, when THS3091 is powered by +/-15V and works at high frequency, and the output signal amplitude is large, the current can reach above 50mA. At this time, the power consumption of the chip is more than 1.5W. When using a chip without a heat sink pad, the temperature rise will be very high. The thermal resistance on the chip datasheet is tested on a board defined by the JEDEC standard. Generally, the actual circuit board heat dissipation may not be that good,
The chip datasheet generally gives a maximum junction temperature of 150°C. However, for chips that work for a long time, the junction temperature cannot exceed 125°C. Below is the maximum junction temperature parameter given in the THS 3091 datasheet.
This concludes the series.
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