Regarding loop compensation, this article is enough[Copy link]
As an engineer, I work with power supply design engineers every day. I find that no matter they are veterans, experts or novices, they are almost at a loss when it comes to the design of the control loop and basically rely on experiments. It is certainly possible to rely on experiments, but when problems arise, it is often difficult to start. Here I would like to take the flyback power supply as an example (the loop is the most difficult among all topologies due to the existence of RHZ) and roughly explain how to calculate it, so that at least everyone can analyze the solution to the problem theoretically when there is a problem.Schematic diagram:
The principle representation of the right half plane zero point is given here, which is very useful for simulation with PSPICE and can be directly applied to this figure.
Write the transfer function yourself. It's a good exercise. The output voltage divided by the input voltage is the transfer function.The Bode plot can easily determine the stability of the circuit and even determine the closed-loop response of the circuit, which shows the gain and phase changes of the zeros and poles shown in the figure below.Single-pole compensation:
It is suitable for current-mode control and power supplies working in DCM mode and with low ESR zero frequency of filter capacitors. Its main working principle is to reduce the control bandwidth and reduce the gain to 0dB before the phase of the power part or the part with other compensation reaches 180 degrees, which is also called main pole compensation.
Double-pole, single-zero compensation is suitable for compensation where the power part has only one pole. Such as: all current-type control and discontinuous voltage-type control.
Three-pole, double-zero compensation is suitable for topologies with LC resonance output, such as all inductor current continuous mode topologies without current mode control.
The main function of C1 is to improve the phase with R2. Of course, it improves the low-frequency gain. The smaller the better while ensuring stability. C2 adds a high-frequency pole to reduce switching noise interference.The essence of connecting C1 in series is to add a zero point. The role of the zero point is to reduce the peak time and speed up the system response. The closer the closed loop is to the imaginary axis, the better the effect. So in theory, the larger C1 is, the better. But we must consider the overshoot and adjustment time, because the closer the zero point is to the imaginary axis, the larger the closed-loop zero point correction coefficient Q is, and Q is proportional to the overshoot and adjustment time, so it cannot be too large. In short, the closed-loop zero point must be considered as a compromise.The essence of parallel connection of C2 is to add a pole. The role of the pole is to increase the peak time and slow down the system response. So in theory, the larger the C2, the better. But we must take into account that when the zero-order points are close to each other, the system response speed cancels each other out. From this point, it can be explained that the system C1 that we want to respond in time should be large, at least larger than C2.Loop stability criteria:
As long as the phase shift of the entire loop is less than 360 degrees when the gain is 1 (0dB), the loop is stable.
However, if the phase shift is close to 360 degrees, two problems will arise: 1) The phase shift may reach 360 degrees and produce oscillations due to changes in temperature, load and distributed parameters; 2) When it is close to 360 degrees, the step response of the power supply (instantaneous increase or decrease in load) will show strong oscillations, which will prolong the time it takes for the output to stabilize and increase the overshoot. The specific relationship is shown in the figure below.
Therefore, the loop must have a certain phase margin. As shown in the figure, when Q=1, the output is the best, so the optimal value of the phase margin is about 52 degrees, and it is generally taken as more than 45 degrees in engineering. As shown in the following figure:
One thing to note here is that the compensation amplifier works in a negative feedback state, and it has a 180-degree phase shift, so there is only 180 degrees left for the power part and the compensation network. The amplitude margin is automatically satisfied no matter which of the above compensation methods is used, so it is generally not necessary to consider it specifically during design. Since the maximum phase shift caused by this curve is 90 degrees when the gain curve is -20dB/decade, and there is still a 90-degree margin, the final synthesized gain curve should generally be a -20dB/decade part that passes through 0dB. After falling below the 0dB bandwidth, the curve is best at -40dB/decade, so that the gain will rise rapidly, and the gain of the low-frequency part is very high, so that the error of the DC part of the power supply output is very small, and the power supply has a good load and line regulation rate.How to design a control loop? The main circuit is often designed according to application requirements, and the design of the control loop is generally not considered in advance during the design. Our premise is to assume that the main power part has been fully designed, and then discuss the loop design. The loop design generally consists of the following processes:
1) Draw the frequency response curve of the known part.
2) Determine the bandwidth frequency, that is, the 0dB frequency of the gain curve, according to actual requirements and various constraints.
3) Determine the type of compensation amplifier and each frequency point based on the bandwidth frequency determined in step 2). Make the slope of the curve at the bandwidth 20dB/decade, and draw the frequency response curve of the entire circuit.
The above process can also be designed using related software: such as pspice, POWER-4-5-6. Some explanations:
The frequency response curve of the known part refers to the product of all parts except Kea (compensation amplifier), which is added on the Bode plot.
The loop bandwidth is of course expected to be as high as possible, but it is subject to several limitations: a) Shannon sampling theorem determines that it cannot be greater than 1/2Fs; b) the influence of the right half plane zero (RHZ), RHZ varies with input voltage, load, and inductance, and is almost impossible to compensate. We can only design the bandwidth away from it, generally 1/4-1/5 of it; c) The bandwidth of the compensation amplifier is not infinite. When the loop bandwidth is set very high, it will be limited by the inability of the compensation amplifier to provide gain, and the capacitor zero point is affected by temperature, etc. Therefore, the actual bandwidth is generally 1/6-1/10 of the switching frequency.
Flyback design example:
Conditions: Input 85-265V AC, after rectification DC 100-375V Output 12V/5A
When the current type is controlled, the sampling resistor is 0.33 ohms
The following is divided into voltage type and peak current type control to design this power loop. All design sampling points are in front of the output small LC. If the sampling point is behind the small LC, the bandwidth cannot be very high due to the limitation of LC resonant frequency. 1) Current type control.
Assuming 3842 is used, the transfer function is as follows
This figure is the schematic diagram of the compensation amplifier. The frequency of RHZ is 33K. In order to avoid excessive phase shift, the bandwidth is generally taken as 1/4-1/5 of its frequency. We take 1/4 as 8K.
The internal resistance of the output filter capacitor is relatively large, and the zero point formed by its own resistance and capacitance is relatively low, so the phase lag at 8K is relatively small. Phanseangle = arctan (8/1.225) - arctan (8/0.033) - arctan (8/33) = 22 degrees.
In addition, it can be seen that the gain curve at 8K is horizontal, so a single pole compensation can be used directly, which can meet the curve shape of -20dB/decade. R2 and C1 of the compensation part are omitted.
Assuming Rb is 5.1K, then R1 = [(12-2.5)/2.5] * Rb = 19.4K.
The gain of the power part at 8K is -20*log (1225/33) + 20*log19.4 = -5.7dB because the bandwidth is 8K, that is, 0dB at 8K.
Therefore, the compensation amplifier gain at 8K should be 5.7dB, 5.7-20*log(Fo/8)=0Fo is the compensation amplifier 0dB gain frequency Fo=1/(2*pi*R1C2)=15.42.
The internal resistance of the output filter capacitor is relatively large, and the zero point formed by its own resistance and capacitance is relatively high, so the phase lag at 8K is relatively large.
If single-pole compensation is still used, the phase margin at the bandwidth is 180-90-47 = 43 degrees, which is too small. Use type 2 compensation to improve it.
The first pole is at the origin, and the first zero is generally taken at about 1/5 of the bandwidth, so that the phase is improved by about 78 degrees at the bandwidth. The lower the zero point, the more obvious the phase improvement, but if it is too low, the low-frequency gain will be reduced, and the output adjustment rate will be reduced. Here we take 1.6K. The second pole is generally selected to offset the gain increase caused by the ESR zero point or the RHZ zero point to ensure the gain margin. We use it to offset the ESR zero point to keep the shape of -20db/10decade at the bandwidth. We take the ESR zero frequency as 5.3K.
Numerical calculation:
The gain of the power part at 8K is -20*log(5300/33)+20*log19.4=-18dB.
Because the bandwidth is 8K, that is, the final synthetic gain curve is 0dB at 8K
, so the gain of the compensation amplifier at 8K should be 18dB, and the gain at 5.3K = 18+20log(8/5.3) = 21.6dB. The horizontal part gain = 20logR2/R1 = 21.6.
fo is the LC resonant frequency. Note that the Q value is not a calculated value, but an empirical value, because the calculated Q cannot take into account the loss of the LC series circuit (equivalent to resistance), including capacitor ESR, diode equivalent internal resistance, leakage inductance and winding resistance and adhesion effect, etc. In actual circuits, the Q value is almost impossible to be greater than 4-5.
Since there is LC resonance in the output, the phase changes dramatically at the resonance point and will quickly approach 180 degrees, so a type 3 compensation amplifier is needed to improve the phase. The principle of placing zeros and poles is as follows: there is a pole at the origin to increase the low-frequency gain, and two zeros are placed at the double poles, so that the phase at the resonance point is -90+(-90)+45+45=-90. Place a pole at the ESR of the output capacitor to offset the influence of the ESR, and place a pole at the RHZ to offset the increase in high-frequency gain caused by RHZ.Component value calculation, for convenience we redraw the diagram of type 3 compensation.
The blue part is the power part, the green part is the compensation part, and the red part is the whole open-loop gain.
If the phase margin is not enough, the two zero positions can be appropriately advanced, or the first pole position can be placed a little later.
Also, assuming that the optocoupler CTR = 1, if an optocoupler with a large CTR is used, or other amplifiers are added, such as the internal op amp of the IC, you only need to add a DC gain to the Bode diagram and then design the compensation part. At this time, it is required to configure the IC internal op amp as a proportional amplifier. If compensation is added to the internal op amp, it will be a little troublesome. Add another compensation line to the diagram to end.
I think everyone should know where to change when there is a problem even if they can't calculate after reading it.ENDCopyright belongs to the original author. If there is any infringement, please contact us to delete it.
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