About SAR ADC front-end conditioning

呜呼哀哉

About SAR ADC front-end conditioning [Copy link]

I am a newbie, so some of my understanding is a bit stubborn, please forgive me. I would like to ask you a few questions.

1. The definitions and abbreviations of each time period in the SAR ADC conversion process are different for different manufacturers on the ADC chip DATAsheet.

2. Is the sample-and-hold circuit of the SAR ADC the same as the recommended model, where the switch of the model is closed upon receiving the conversion instruction, and the sample-and-hold circuit is disconnected after the holding capacitor is fully charged? Or is it disconnected after the conversion is completed?

3. Combined with the results of 2, can the description in ADI's technical article be explained?

The maximum change rate of the sinusoidal signal mentioned above is understood. The problem is that the external capacitor and the ADC input capacitor are connected in parallel, which can indeed cause the capacitor voltage change in the figure. Once the sample and hold circuit is disconnected, the external op amp circuit has sufficient full-power bandwidth, and the voltage change on the external capacitor still changes according to the maximum change rate of the sinusoidal signal. Where is this based on the reduction of step change by connecting capacitors in parallel?

呜呼哀哉

Is the section in the wrong place? Why didn't anyone reply? If the description of the problem is not clear, please add more.

littleshrimp

Look at this paragraph

littleshrimp

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The definitions and abbreviations of the various time periods in the conversion process vary from manufacturer to manufacturer, and there seems to be no unified international standard.

Jacktang

Jacktang

Since the problem is indeed as the poster said, it is quite stubborn. I suggest the poster to read the following sharing by TI FAE

Rafael, a senior application engineer of TI's SAR-ADC, once said that 70%-80% of the emphasis of SAR-ADC application circuit design should be placed on the design of the reference source circuit. However, engineers often ignore the design of the reference source circuit.

The reason why this problem is often overlooked may be due to the textbooks we used during college. In many textbooks on "Basics of Digital Circuits", the capacitor network structure inside the SAR-ADC is generally not given, and textbooks on "Basics of Analog Circuits" rarely discuss reference sources. However, the circuit design of the reference source is crucial when designing a SAR-ADC. Simply put, if the reference is not accurate, clean, and stable, there is no need to expect the converted result to be accurate. The following will illustrate the importance of reference source design from the internal structure of the ADC and the design points of the reference circuit, and provide a reference circuit design that supports 16-bit SAR-ADC.

The following figure is a simplified diagram of the internal principle of the SAR ADC. During the sampling process, the SAR-ADC input pin AIN charges the internal sampling capacitor. During the conversion process, the Vref reference source pin charges the conversion capacitor network. In short, the sampling and holding and quantization processes of the SAR-ADC are both charging processes for the internal capacitor. Engineers who have read the related article "Design SAR-ADC Driver Cirtuitry" will deeply understand the importance of the ADC input pin capacitor after the SAR-ADC driver circuit. The reason is that during the sampling and holding process, the SAR-ADC sampling capacitor will extract charge from the input pin AIN driver capacitor.

Several parts

The 80% of the key points that are often overlooked, SAR-ADC voltage reference circuit [TI FAE sharing]

The 80% of the key points that are often overlooked, SAR-ADC voltage reference circuit part II

The 80% of the key points that are often overlooked, SAR-ADC voltage reference circuit part III

The 80% of the key points that are often overlooked, the final key to the SAR-ADC voltage reference circuit part IV

呜呼哀哉

littleshrimp posted on 2021-3-29 16:36 Take a look at this

Thank you very much, one problem has been solved, it is indeed the switch that is closed and then opened and then switched.

Then there is another question. The rate of change after signal conditioning is determined by the output amplitude and frequency. There is no problem. There is no problem with the capacitor voltage change caused by the parallel connection of the internal capacitor of the ADC and the capacitor of the analog signal conditioning part. The problem is that after the switch is closed and opened, the external voltage change in the conversion stage is determined by the signal amplitude and frequency, so the capacitor parallel attenuation change does not seem to exist. It is also possible that during your conversion stage, the external signal is just at the maximum conversion position.

呜呼哀哉

Jacktang posted on 2021-3-29 21:15 Since the problem is indeed as the original poster said, it is quite stubborn. I suggest the original poster read the following sharing by TI FAE. Raf, a senior application engineer in SAR-ADC at TI ...

Thank you, I will go to TI official website to find these materials and study them

littleshrimp

Alas, published on 2021-3-29 21:18 Thank you very much, one problem has been solved, it is indeed the switch closed and then opened and then converted. Then another question, the rate of change after signal conditioning determines...

The voltage measured by the ADC is the voltage during the sampling period. The voltage change during the conversion period theoretically has no effect on the data, so it is common to see applications using multiple ADCs to alternately sample to increase the sampling rate.

呜呼哀哉

littleshrimp posted on 2021-3-30 13:02 The voltage measured by the ADC is the voltage during the sampling period. The voltage change during the conversion period will not affect the data in theory, so we often see the use of multiple...

Thanks, I read some information these days.

The value measured by the ADC is the value at the moment of sampling.

In addition, the parallel attenuation step of the external capacitor and the ADC input capacitor means that the value of the last sampling is held by the internal capacitor of the ADC, and the value on the external capacitor in the next sampling is not equal to the holding capacitor. The external capacitor is the real value, and the holding capacitor is the last value. They decay in parallel and quickly build on the real value of the second sampling.