【GD32E503 Review】GD32E503VET6 Performance Test

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【GD32E503 Review】GD32E503VET6 Performance Test [Copy link]

 

2.4 GD32E503VET6 Performance Test
2.4.1 Preliminary Analysis of Indicators
When developing products using GD32E503, R&D engineers will basically consider two indicators: power consumption and performance.
Power consumption is very difficult to calculate, and it is related to the frequency of hardware use, environment, and program. According to the functional interface, the power consumption of the microcontroller is divided into the following categories: internal power consumption (related to frequency), digital input and output ports, input ports, analog interfaces, etc. We directly quote the GD32E5032 datasheet, and the query data is as follows:

How to comprehensively consider the various aspects of GD32E503 performance? In the field of embedded processors, common methods for testing CPU performance are: Dhrystone and CoreMark. The Dhrystone method is old and has not been updated. I have not successfully transplanted it, so this article will use the CoreMark test method.
The CoreMark standard was proposed by Shay Gla-On of the EEMBC organization in 2009, and attempts to develop it into an industry standard to replace the old Dhrystone standard.
CoreMark is a simple, yet sophisticated benchmark that is designed specifically to test the functionality of a processor core. Running CoreMark produces a single-number score allowing users to make quick comparisons between processors.
CoreMark is a score obtained by running C language code. It mainly includes the following algorithms: enumeration (search and sort), mathematical matrix operations (normal matrix operations) and state machines (used to determine whether the input stream contains valid numbers), and finally CRC (cyclic redundancy check).
2.4.2 CoreMark core program
Refer to the CoreMark official website for information, address: https://www.eembc.org/coremark/index.php
The latest version is 1.0.

2.4.3 GigaDevice official development package
Download GigaDevice GD32E50x_Demo

2.4.4 The integrated development environment is IAR EWARM

Fig 33 IAR version diagram
2.4.5 Porting CoreMark program
First, select a complete template and configure the serial port routine 04_USART_Printf in the demo routine as a template to simplify the configuration process.

Fig 34 Development board UART0 schematic diagram
Since the processor operating frequency of the core chip GD32E503VET6 of the GD32E503V-EVAL development board is up to 180MHz, it is recommended to set the main frequency to 180M. I did not modify it.
Change the stack size during initialization to a larger size, otherwise there will be problems. The default is 0X00000800, and I changed it to 0X00002000 here.
Open options > linker > Override default > Edit, and change it to: 0x2000 [attach] 521933 [/attach]
Create a new Coremark folder and add the Coremark program
[attach] 521934 [/attach]
Add files to the project and include the header file path
[attach] 521935 [/attach]
(1) Add initialization code to Core_portme.c
1) portable_init function
The portable_init function in Core_portme.c is first called in the main function of Core_main.c. The platform initialization function (clock, GPIO, serial port) can be placed here. Copy the initialization code in the Main function to the portable_init function.

2) Add variables and functions
#define SysTick_Counter_Disable ((uint32_t)0xFFFFFFFE)
#define SysTick_Counter_Enable ((uint32_t)0x00000001)
#define SysTick_Counter_Clear ((uint32_t)0x00000000)
__IO uint32_t Tick;
3) Add header file

4) Delete the main function, because Core_main.c has a main function
5) Modify the timer code
start_time/ stop_time/ get_time These functions are used to calculate the program running time when the coremark program is running. Here, the system tick is used for timing, and the system tick is configured as an interrupt interval of 1ms. The value of Tick is updated in the system tick interrupt function, and it is increased by 1 every time an interrupt is entered. Therefore, we also need to modify the interrupt processing function of the system tick. In Core_portme.c, find the place that needs to be modified according to the table below:
start_time(void)
{
//GETMYTIME(&start_time_val);
Tick=0;
SysTick_Config(SystemCoreClock/1000);
}
stop_time(void)
{
//GETMYTIME(&stop_time_val);
SysTick->CTRL&=SysTick_Counter_Disable;
SysTick->VAL=SysTick_Counter_Clear;

}
get_time(void)
{
CORE_TICKS elapsed=(CORE_TICKS)Tick;
return elapsed;
}
6) 注释无用语句
//#define NSECS_PER_SEC CLOCKS_PER_SEC
//#define CORETIMETYPE clock_t
//#define GETMYTIME(_t) (*_t = clock())
//#define MYTIMEDIFF(fin, ini) ((fin) - (ini))
//#define TIMER_RES_DIVIDER 1
//#define SAMPLE_TIME_IMPLEMENTATION 1

//static CORETIMETYPE start_time_val, stop_time_val;
7) 其他
#define EE_TICKS_PER_SEC 1000

Associated printf function

/* retarget the C library printf function to the USART */

int fputc(int ch, FILE *f)

{

usart_data_transmit(EVAL_COM0, (uint8_t)ch);

while (RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));

return ch;

}

(2) Modify the systick.c function

(3) Run configuration
CoreMark requires that the program run time is at least 10 seconds. Depending on the system clock used, the number of iterations can be modified in Core_portme.h.
#define ITERATIONS 12000
(4) CoreMark run configuration
1) Set the number of iterations
CoreMark requires that the program run time is at least 10 seconds. Depending on the system clock used, the number of iterations can be modified in Core_portme.h.
#define ITERATIONS 12000
2) Set the print information
According to the specific compiler version used, optimize the configuration and modify it. Modify in Core_portme.h
Find COMPILER_FLAGS and modify it to
#ifndef COMPILER_FLAGS
#define COMPILER_FLAGS "-Ohs -no_size_constraints"
#endif

3) Optimization level

2.4.6 CoreMark Results

（我没有修改主频，结果如下；）
2K performance run parameters for coremark.
CoreMark Size : 666
Total ticks : 23833
Total time (secs): 23.833000
Iterations/Sec : 503.503546
Iterations : 12000
Compiler version : Please put compiler version here (e.g. gcc 4.1)
Compiler flags : -Ohs -no_size_constraints
Memory location : STACK
seedcrc : 0xe9f5
[0]crclist : 0xe714
[0]crcmatrix : 0x1fd7
[0]crcstate : 0x8e3a
[0]crcfinal : 0xd340
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 503.503546 / Please put compiler version here
(e.g. gcc 4.1) -Ohs -no_size_constraints / STACK

w494143467

Thanks for sharing!