CC2640RF Debug Interface (cJTAG)

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CC2640RF Debug Interface (cJTAG) [Copy link]

cJTAG stands for Compact Joint Test Action Group, which is a superset of JTAG (Joint Test Action Group).
IEEE1149.1 defines the JTAG standard, which was officially released in 1990. With the advancement of semiconductor chip technology, multi-chip packaging, ultra-low power consumption and other increasingly complex designs, JTAG seems to be a bit stretched. There is an urgent need for a solution, so cJTAG was born, which is backward compatible. Of course, in addition to JTAG, there is also SWD (serial wire debug), which is
the four new features of cJTAG designed by ARM:
1. Provide power management. Previously, there was only the "Alwasy On" mode, but now it can provide support for super power consumption device mode.
2. Support for increased chip integration.
3. Application debugging.
4. Device programming.
cJTAG (IEEE1149.7) functions are divided into 6 levels of classes, each of which is a superset of all lower classes:
T0: Based on supporting IEEE1149.1 (JTAG), add support for multi-chip traversal.
T1: Basic functions of Tap.7 controller, some functions are extended, and power consumption logic control is supported.
T2: Support chip-level bypass in serial scan series.
T3: 4-wire mode star scan topology.
T4: 2-wire or 4-wire star scan topology. Use advanced protocols to transmit data, and TDIC and TDOC pins can be used for other purposes or not used.
T5: Custom communication protocol expansion. Use advanced protocols and 8 data channels to transmit background data.
Summary:
Classes T0 to T3 occupy the original IEEE1149.1 standard and show more functions.
Classes T4 and T5 focus on two-pin system operations rather than the operations required by the original JTAG.
Both JTAG and cJATGd use boundary scan technology to implement debugging.

JTAG requires the following pins:
TCK: Test clock.
TMS: Test mode select.
TDI: Test data input.
TDO: Test data output.
TRST: Test reset, which is an optional pin.

Pins required by cJTAG:
In the high-level protocol of cJTAG, TDI, TMS, and TDO information are converted into scan packets (SP) format and transmitted on the TMSC pin. TAPC extracts information from SP for testing.
TMSC: Data transmission pin, which is a bidirectional transmission IO.
TCKC: Mainly responsible for the debugger clock output to the debugging device.
TDIC, TDOC: Optional pins used for other purposes or not used.

CC2640R2F supports cJTAG and JTAG, and using only TMSC and TCKC is the default configuration after power-on.