MSP430F5529 Unified Clock System UCS

火辣西米秀

MSP430F5529 Unified Clock System UCS [Copy link]

A module clock source: MODOSC, generates the MODCLK clock source signal, and generally only serves the flash memory control module and the ADC12 module.

This module is automatically turned off when not in use. When any module requests the use of this clock source, MODOSC can respond to the request without being enabled. The MODCLK in 430F5529 is 5MHZ.

*************************************************** *************

MSP430F5529 has multiple clock sources, and the clock sources of many modules can be freely selected. In addition, because in general, system power consumption is proportional to the operating frequency, sometimes by selecting a lower frequency clock source, under normal working conditions, it is possible to effectively reduce power consumption. Although the function library HAL_UCS.c/h has complete control functions, I think it is simpler to operate the registers directly for this chapter, because the functions are too short and there are too many of them.

　　3.1 Introduction to the Unified Clock System (UCS)

Unified Clock System, UCS. Reasonable clock configuration can achieve the purpose of balancing the system and reducing power consumption.

The MSPF5529 clock system includes 5 clock sources:

①LFXT1 external low frequency oscillator source, 32.768KHZ, can be used as a reference source for FLL;

　　②XT2 external high frequency oscillation source, 4MHZ;

　　③VLO (Internal very low): internal low-power low-frequency oscillation source, typically 10KHZ, with average accuracy;

　　④REFO internal low frequency reference source, 32.768KHZ, often used as the reference frequency of the phase-locked loop FLL, with high accuracy, no power consumption when not in use, its setting often refers to the setting of LPM mode;

　　⑤DCO (Internal digitally-controlled) internal digital control oscillator source, usually set by FLL; (very useful, very important, will be discussed in detail later)

　　Three clock signals are usually used, all of which come from the five signal sources mentioned above:

　　①ACLK (Auxiliary clock), the clock source can be selected from XT1, REFOC, VLO, DCO, DCOCLKDIV, XT2 by software control. DCOCLKDIV is obtained by dividing DCO by 1, 2, 4, 8, 16 or 32. Note that ACLK can also be divided by 1, 2, 4, 8, 16 or 32 again.

　　②MCLK (Master clock) is the main clock, and its characteristics are exactly the same as ACLK.

　　③SMCLK (Subsystem master clock) subsystem clock, its characteristics are exactly the same as ACLK.

　　3.2 UCS Operation Instructions

The default clock status when the machine is powered on is (must be remembered clearly!!!):

ACLK: XT1 (low frequency mode is selected as XT1CLK clock oscillator, XT1CLK is selected as the clock source 32.768KHZ of ACLK)

MCLK: DCOCLKDIV (1.048576MHZ, DCOCLK = 2.097152MHZ)

SMCLK: DCOCLKDIV (1.048576MHZ)

In addition, the reference source of FLL defaults to XT1;

　　 If the pins connected to XT1 and XT2 are not set with PXSEL, then both clock sources are invalid;

　　 REFOCLK, VLOCLK, and DCOCLK are available by default;

　　After the system is stable, the default value of DCOCLK is 2.097152MHZ, and the default frequency division of FLL is 2, so the frequency of MCLK and SMCLK is 1.048576MHZ. (How to calculate will be mentioned in Experiment 3)

　　In addition, the selection of system reset and system working mode LPM will have a certain impact on UCS. There are too many restrictions here. For details, please refer to the UCS part of TI official data. LPM and system reset will be discussed in the next chapter.

A brief summary of the operating instructions: (The following is basically nonsense, just understand it)

　　①The choice of VLO is the simplest and does not need to take other conditions into consideration;

　　②The selection of REFO needs to refer to different working modes and has various restrictions;

　　③XT1 and XT2 have the same features. When using them, you must not only configure the pins connected to them, but also the capacitors, and pay attention to whether they work in low-frequency or high-frequency mode. Moreover, there are different requirements in different working modes;

　　④ As a digitally controlled oscillator, the frequency of DCO can be adjusted not only by itself but also by the FLL phase-locked loop.

　　⑤FLL phase-locked loop is a flexible choice for frequency conversion. It can set the reference frequency, select the frequency division number, and can be directly turned off to achieve the purpose of reducing power consumption;

　　⑥UCS system has clock signal error protection mechanism;

　　⑦ For places with strict timing requirements, choose a high-precision clock source and make good modulation settings for the FLL and DCO parts;

　　⑧ Clock control diagram in different modes (some clock sources are prohibited): (Just pay attention when you use it, check the table)

　　3.3 UCS Register Control Operation

There are 10 groups of 16-bit read and write registers, UCSCTL0-UCSCTL9. Word and byte operations are also supported, that is, UCSCTL0 includes UCSCTL0_H and UCSCTL0_L.

Note: Any bit marked "Reserved" will be treated as 0 when read back unless otherwise stated.

　　UCSCTL0

　　DCO: DCO frequency selection. The DCO frequency is selected and automatically adjusted during FLL operation (due to changes in the MOD bits). The 5 control bits of DCO divide the DCO frequency selected by DCORSELx into 32 equal parts, with an interval of approximately 8%.

　　MOD: Modulation bit counter. Select the modulation type, all MOD bits are automatically adjusted during FLL operation without user intervention.

　　UCSCTL1

DCORSEL: DCO frequency range selection

　　DISMOD: Modulator disable enable bit. 0—Enable the modulator; 1—Disable the modulator.

　　UCSCTL2

　　FLLD: Prescaler (i.e. fDCO division). 000-1 division, 001-2 division, 010-4 division, 011-8 division, 100-16 division, 101-32 division, 110 and 111 are all spare, the default is 32 division.

　　FLLN: frequency multiplication factor. Set the frequency multiplication value N, N must be greater than 0. If FLLN=0, N is automatically set to 1.

　　UCSCTL3

　　SELREF: FLL reference clock selection. 000-XT1, 001-standby, default is XT1, 010-REFO, 101-XT2, the rest are standby, default is REFO.

　　FLLREFDIV: FLL reference clock divider. 000-1, 001-2, 010-4, 011-8, 100-12, 101-16, 110 and 111 are all spare, the default is 16.

　　UCSCTL4

　　SELA: ACLK clock source selection. 000-XT1, 001-VLO, 010-REFO, 011-DCO, 100-DCOCLKDIV, 101-XT2 is XT2 when XT2 is valid, otherwise it is DCOCLKDIV 110, 111 are reserved for later use. When XT2 is valid, it defaults to XT2CLK, otherwise it defaults to DCOCLKDIV

　　SELS: SMCLK clock source selection. The setting is the same as SELA

　　SELM: MCLK clock source selection. Setting is the same as SELA

　　UCSCTL5

　　DIVPA: ACLK external valid output division 000-1 division, 001-2 division, 010-4 division, 011-8 division, 100-16 division, 101-32 division, 110 and 111 are spare, the default is 32 division.

DIVA: ACLK clock source frequency division, setting is the same as DIVPA

DIVS: SMCLK clock source frequency division, setting is the same as DIVPA

DIVM: MCLK clock source frequency division, setting is the same as DIVPA

UCSCTL6

　　XT2DRIVE: XT2 oscillator current drive capability adjustment, 00 minimum current consumption. XT2 oscillator operates at 4MHz to 8MHz…

　　XT2BYPASS: XT2 bypass selection 0-XT2 comes from internal clock (using external crystal oscillator) 1-XT2 comes from external pin input (bypass mode)

　　XT2OFF: Turn off XT2 oscillator 0 - When the XT2 pin is set to XT2 function and is not set to bypass mode, XT2 is turned on; 1 - When XT2 is not used as a clock source and is not used as FLL reference clock, XT2 is turned off.

　　XTS: XT1 operating mode selection 0- low frequency mode (XCAP defines the capacitance between XIN and XOUT pins) 1- high frequency mode (XCAP bit is not used)

　　XCAP: Oscillator Load Capacitor Selection

　　SMCLKOFF: SMCLK off control bit 0-SMCLK on 1-SMCLK off

　　XT1OFF: Same as XT2OFF

UCSCTL7

　　XT2OFFG: Set when XT2 fails, and OFFIFG will also be set, which needs to be cleared by software.

　　XT1HFOFFG: Set when XT1 fails in high-frequency working mode, and OFFIFG will also be set, which needs to be cleared by software.

　　XT1LFOFFG: Set when XT1 fails in low-frequency operating mode, and OFFIFG will also be set, which needs to be cleared by software.

　　DCOOFFG: Set when DCO makes an error, but also when DCO=1 or 31, it is set, and OFFIFG is also set, which needs to be cleared by software.

　　UCSCTL8

　　Signal request enable: 0-corresponding signal request is prohibited 1-corresponding signal request is allowed

　UCSCTL9

　　XT1, XT2 bypass mode input swing level (range) must be set 0-input range 0~DVCC 1-input range 0~DVIO

3.4 Experimental Summary

Experiment 1: Configure MCLK and SMCLK as REFOCLK and VLOCLK (oscilloscope measurement required)

/* REFOCLK and VLOCLK are provided by default by the chip. As long as the chip works normally, these two clocks will work normally. Therefore, the clock configuration is very simple. You only need to modify UCSCTL4 and configure SELS and SELM to the corresponding options VLOCLK or REFOCLK*/

#include

void main(void){

WDTCTL = WDTPW + WDTHOLD;

P1SEL |= BIT0; //Declare a special function and will not be used as a normal I/O

P1DIR |= BIT0; //ACLK output terminal, used to measure ACLK frequency, external frequency meter

P2SEL |= BIT2;P2DIR |= BIT2;//SMCLK output

P7SEL |= BIT7;P7DIR |= BIT7; //MCLK output terminal

//UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //Configure SMCLK and MCLK as VLOCLK

UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //Configure SMCLK and MCLK as REFOCLK

/* UCSCTL4&(~(SELS_7|SELM_7)) This statement is equivalent to clearing SELS and SELM first*/

while(1);

}