MSP430F5438 study notes DCO frequency multiplication to 8MHZ

火辣西米秀

MSP430F5438 study notes DCO frequency multiplication to 8MHZ [Copy link]

// Clock default
// FLL clock FLL selects XT1
// Auxiliary clock ACLK selects XT1 32768Hz
// Main system clock MCLK selects DCOCLKDIV 1048576Hz
// Subsystem clock SMCLK selects DCOCLKDIV 1048576Hz
#include <msp430.h>
void clock_config(void);
void select_xt1(void);
void dco_config(void);

int main(void)
{
clock_config(); // Initialize clock

P4DIR |= BIT0; // P4.0 output

while(1)
{
P4OUT ^= BIT0;
__delay_cycles(1000000);
}
}

void clock_config(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog
select_xt1(); // Select XT1
dco_config(); // ACLK = XT1 = 32.768K
// MCLK = SMCLK = 8000K
}

void select_xt1(void)
{
// Start XT1
P7SEL |= 0x03; // P7.0 P7.1 peripheral function
UCSCTL6 &= ~(XT1OFF); // XT1 turn on
UCSCTL6 |= XCAP_3; // internal capacitor
do
{
UCSCTL7 &= ~XT1LFOFFG; // clear XT1 error flag
}while (UCSCTL7&XT1LFOFFG); // detect XT1 error flag
}

void dco_config(void)
{
__bis_SR_register(SCG0); // disable FLL function
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // DCO maximum frequency is 16MHz
UCSCTL2 = FLLD_1 + 243; // set DCO frequency to 8MHz
// MCLK = SMCLK= Fdcoclkdiv = (N+1)X(Ffllrefclk/n)
// N is the only value that needs to be calculated
// Ffllrefclk FLL reference clock, default is XT1
// n takes the default value, which is 1
// (243 + 1) * 32768 = 8MHz
__bic_SR_register(SCG0); // Enable FLL function

// Necessary delay
__delay_cycles(250000);

// Clear error flags
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear all oscillator error flags
SFRIFG1 &= ~OFIFG; // Clear oscillator error
}while (SFRIFG1&OFIFG); // Wait for clearing to complete
}