msp430f5529 capture plus serial port source code

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msp430f5529 capture plus serial port source code [Copy link]

msp430f5529 capture plus serial port, can be used for everyone to learn

The microcontroller source program is as follows:

#include "msp430f5529.h"

#define uint unsigned int
#define uchar unsigned char

uint flag,TA_cent,PerVal;
unsigned long int val,cha;
int m[5];
void Delay10ms(unsigned int c) //误差 0us
{
unsigned char a, b;

//--c has been assigned a value when it was passed, so there is no need to assign a value in the first sentence of the for statement--//
for (;c>0;c--)
{
for (b=38;b>0;b--)
{
for (a=130;a>0;a--);
}
}
}
void USCI_A0_Init() //Initialization of USCI_A0
{
P3SEL |= BIT3+BIT4; // P3.3 and P3.4 select UART communication function
UCA0CTL1 |= UCSWRST; // Reset register setting
UCA0CTL0 = 0x00;
UCA0CTL1 |= UCSSEL_1; // Baud rate generator reference clock is set to ACLK, ACLK=32768Hz
UCA0BR0 = 0x03; // Baud rate is set to 9600bps
UCA0BR1 = 0x00;
UCA0MCTL |= UCBRS_3 + UCBRF_0; // Modulator settings
UCA0CTL1 &= ~UCSWRST; // Complete USCI_A0 initialization settings
}
void fasongzifu (char Cha) // Single character sending function
{

UCA0TXBUF = Cha;
while (!(UCA0IFG&UCTXIFG)); //Wait for the last byte to be sent
}

//void yunsuan()
//{
//int m[5];
//m[0]=val%10000/1000;
//m[1]=val%1000/100;
// m[2]=val%100/10;
//m[3]=val%10;
//m[4]='.';
// USCI_A0_Putchar(m[0]+48);
//USCI_A0_Putchar(m[4]);
//USCI_A0_Putchar(m[1]+48);
//USCI_A0_Putchar(m[2]+48);
//USCI_A0_Putchar(m[3]+48);
//}

void main( void )
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;

P1DIR&=~BIT2; //Capture P1.2 port
P1SEL |= BIT2;
TA0CCTL1 |= CAP + CM_1 + CCIS_0 + SCS + CCIE; //Capture mode, capture both rising and falling, select CCI2A, synchronous, disconnect during capture
TA0CTL |= TASSEL_2 + MC_2 + ID_0 + TAIE + TACLR; //SMCLK=1M, continuous counting mode

USCI_A0_Init(); //USCI_A0 initialization

_EINT(); //Interrupt start bit
while(1);
}

#pragma vector=TIMER0_A1_VECTOR
__interrupt void TIMER0_A1_ISR(void)
{
switch(TA0IV)
{
case 2:
val = TA0CCR1 - PerVal;
PerVal = TA0CCR1;
flag++;
if(flag >2)
{
flag =0;
val = 1048576 / val; //1048576: After the system is stable, the DCOCLK defaults to 2.097152MHZ, and the FLL defaults to 2 division, then the frequencies of MCLK and SMCLK are both 1.048576MHZ. (How to calculate will be mentioned in Experiment 3)
m[0]=val%10000/1000;
m[1]=val%1000/100;
m[2]=val%100/10;
m[3]=val%10;
m[4]=' ';
fasongzifu(m[0]+48);
fasongzifu(m[1]+48);
fasongzifu(m[2]+48);
fasongzifu(m[3]+48);
fasongzifu(m[4]);
Delay10ms(10);

}
TA1CCTL0 &= ~CCIFG;
break;
case 4:
break;
case 10:
TA1CCTL0 &= ~CCIFG;
break;
}
}

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