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LNA Design of ATF54143 [Copy link]

This article designs LNA based on the ATF54143 chip. The ATF54143 chip is an LNA chip formerly developed by Agilent. It has the characteristics of high gain, high linearity and low noise. It is widely used in base station scenarios with a frequency coverage range of 450MHz-6GHz.

According to the characteristics of DataSheet, this article first sets the static operating point. The static operating point is set according to the working voltage Vdc=5V, Vgs=0.5V, Vds=5V, ids=60mA. The specific static operating point setting circuit reference is as follows:

The static circuit simulation results are as follows, satisfying the stability coefficient K>1, the noise coefficient N<1, and the maximum gain (1.5GHz) is 19dB.

This article designs according to the parameters of maximum gain. It is necessary to find the input and output impedances when designing the maximum gain. The impedances are as follows:

The Ga circle corresponds to the impedance of Zs, and the Gp circle corresponds to the impedance of ZL. In this way, we can design the input and output matching. The maximum gain design must satisfy the conjugate matching, and the matching diagram must meet the requirements of the figure below.

First, design the input matching:

Impedance matching design can be operated by opening the Smith Chart tool in ADS. Set one impedance to 50 ohms and the other impedance to 7.6+j*4.56. The reference diagram is as follows:

Its input matches are as follows:

The S parameter simulation results are as follows, which meet the requirements very well:

Similarly, the output matching is also carried out in the above manner. The matching method is designed according to the low-pass method, which can effectively suppress high-frequency harmonics, etc.

The entire simulation schematic is as follows:

All simulation results:

Finally, the layout simulation is carried out. The layout simulation requires the improvement of the schematic diagram, that is, additional routing is needed between components to connect the layout. The premise of the perfect layout schematic diagram is to meet the requirements of the tube work.

The generated layout is as follows. The layout needs to be adjusted according to the actual position and needs to be as beautiful as possible.

After the layout is completed, an EM model is generated for joint simulation.

Due to the influence of parasitic parameters, the joint simulation requires local fine-tuning of the matching and comparison.

This article combines the ATF54143 tube. What needs to be considered is the design of the static operating point. It is necessary to understand how each component affects the impedance, noise factor, stability and maximum gain. It is necessary to master the input and output matching design, and it is necessary to master how to make and optimize the layout.

This post is from RF/Wirelessly

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Thanks for sharing   Details Published on 2020-7-24 20:17
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Thanks for sharing

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