1 System Overview
As shown in the figure, this is the principle block diagram of the entire video acquisition system. At the beginning of power-on, the FPGA needs to initialize the register configuration of the CMOS Sensor through the IIC interface . These basic initialization parameters, that is, the initialization data corresponding to the initialization address are stored in a pre-configured FPGA on-chip ROM . After the initialization configuration is completed, the CMOS Sensor can continuously output a standard RGB video data stream. The FPGA detects its synchronization signals, such as clock, line frequency, and field frequency, to collect image data from the data bus in real time. The MT9V034 camera can output a normal video stream by default initialization data, so no IIC initialization configuration is actually performed in the FPGA .
Inside the FPGA , the collected video data first passes through a FIFO to convert the original synchronous data stream at 25MHz to a frequency of 50MHz . Then the data is sent to the asynchronous FIFO that writes the DDR3 cache . Once the data in this FIFO reaches a certain amount, it will be written to DDR3 through the AXI HP0 bus . At the same time, the AXI HP0 bus will also read the image data cached in DDR3 , cache it in the FIFO , and finally send it to the LCD driver module for display. The LCD driver module continuously sends requests to read image data and drives the LCD display to display video images.
In addition to the DDR3 cache and display of the original image mentioned above, this example also performs multi-line cache and Laplace edge extraction processing on the image before caching the original image to DDR3 to obtain a new image stream, which is written to DDR3 via the AXI HP1 bus . The AXI HP1 bus also reads the processed image for display based on the request of the LCD display module. Finally, on the VGA LCD monitor, you can see that the image on the left is the original image, and the image on the right is the image after edge extraction processing.
2 Image Laplacian edge extraction
2.1 Basic Concepts
In image enhancement, smoothing is to eliminate the interference of noise in the image or reduce the contrast. On the contrary, sometimes in order to emphasize the edges and details of the image, it is necessary to sharpen the image and increase the contrast.
Laplace sharpening is based on the mutation of the surrounding pixels of a certain pixel in the image to this pixel, that is, it is based on the degree of change of the image pixels. We know that the first-order differential of a function describes the direction in which the function image changes, that is, growth or decrease; while the second-order differential describes the speed of the image change, whether it grows or decreases sharply or grows or decreases gently. Based on this, we can guess that the transition degree of the image pigment can be found based on the second-order differential, for example, the transition from white to black is relatively sharp.
Or to put it in more official terms: when the grayscale of the central pixel of the neighborhood is lower than the average grayscale of other pixels in its area, the grayscale of this central pixel should be further reduced; when the grayscale of the central pixel of the neighborhood is higher than the average grayscale of other pixels in its neighborhood, the grayscale of this central pixel should be further increased, so as to achieve image sharpening.
2.2 Laplace operator
The most commonly used non-directional second-order difference operator, its template has various forms such as 3*3 , 5*5 and 7*7 .
For example, taking the 3*3 operator as an example, pixels 1 to 8 are the 8 pixels around the point ( x,y ). You can use the two templates on the right to operate on ( x,y ) and the surrounding 8 pixels to replace the original point ( x,y ).
2.3 Matlab Implementation
Based on the second Laplace edge extraction operator, our Matlab code is as follows:
clear
clc
I1=imread('.\lena.jpg');
I=im2double(I1);
[m,n,c]=size(I);
A=zeros(m,n,c);
%for R
for i=2:m-1
for j=2:n-1
A(i,j,1)=I(i-1,j-1,1)+I(i+1,j-1,1)+I(i-1,j+1,1)+I( i+1,j+1,1)+I(i+1,j,1)+I(i-1,j,1)+I(i,j+1,1)+I(i,j- 1,1)-8*I(i,j,1);
end
end
%for G
for i=2:m-1
for j=2:n-1
A(i,j,2)=I(i-1,j-1,2)+I(i+1,j-1,2)+I(i-1,j+1,2)+I( i+1,j+1,2)+I(i+1,j,2)+I(i-1,j,2)+I(i,j+1,2)+I(i,j- 1,2)-8*I(i,j,2);
end
end
%for B
for i=2:m-1
for j=2:n-1
A(i,j,3)=I(i-1,j-1,3)+I(i+1,j-1,3)+I(i-1,j+1,3)+I( i+1,j+1,3)+I(i+1,j,3)+I(i-1,j,3)+I(i,j+1,3)+I(i,j- 1,3)-8*I(i,j,3);
end
end
B=A;
%output
imwrite(B,'lena.tif','tif');
imshow('.\lena.jpg');title('origin image');figure
imshow('lena.tif');title('image after laplace transform')
The filtering effect is as follows.
The Matlab source code, the original image Lena.jpg and the comparison image are stored in the project\zstar_ex65\matlab folder.
3 Image smoothing processing based on FPGA
The laplace_transform.v module in the project folder project \zstar_ex65\zstar.srcs\sources_1\new implements the Laplace edge extraction of images. The functional block diagram of this module is as follows. Two FIFOs are used to cache the front and back rows respectively, that is, the three groups of data streams entering the image processing are the images of the n-1th row, the nth row , and the n+1th row. The input data stream and the images cached by the two FIFOs are controlled at the same position, and the register caches the image values of the two pixels before and after. In this way, the synchronous processing of the center pixel and the front and back columns, and the upper and lower rows can be realized.
4 Assembly Instructions
The MT9V034 camera module is connected to the Zstar Zynq development board through the Zstar ISB baseboard ( P3 ) , and the VGA is also connected to the Zstar Zynq development board through the Zstar ISB baseboard . The VGA board also needs to be connected to the VGA display. The connection diagram is shown in the figure.
5. Board-level debugging
This example corresponds to the ex65 example project, and the prepared BOOT.bin is placed in the project path "zstar_ex65\zstar.sdk\BOOT" . You can also refer to the document "Playing with Zynq- Example: [ex51] Making the startup file BOOT.bin.pdf for the naked running program " to make a BOOT.bin file containing a .bit file , copy it to the TF card, insert it into the card slot of the Zstar development board, make assembly connections, and power on. You can see that the VGA monitor displays two images on the left and right at the same time. The image on the left is the original image, and the image on the right is the image after Laplace edge extraction processing. This content was originally created by ove,
a netizen on the EEWORLD forum.If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source
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