TMS320F28335 ADC Learning Notes

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TMS320F28335 ADC Learning Notes [Copy link]

1. Correspondence between ADC channel and result register:
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x02U; // Setup ADCINA0 as 1st SEQ1 conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x03U;
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x00U;
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x01U;

ADCINA2 -> AdcRegs.ADCRESULT0;
ADCINA3 -> AdcRegs.ADCRESULT1;
ADCINA0 -> AdcRegs.ADCRESULT2;
ADCINA1 -> AdcRegs.ADCRESULT3;

From the above code, we can see that your channel corresponds to which CONVxx, and the result is stored in which result register AdcRegs.ADCRESULTxx:
CONV00------------------AdcRegs.ADCRESULT0
CONV01------------------AdcRegs.ADCRESULT1
…
CONV15------------------AdcRegs.ADCRESULT15This
correspondence is fixed, and the A/D input channel can choose which four bits of the control register, namely CONVxx, to input and then convert.

2. Why is the value of the result register shifted right by 4 bits?
The result register is 16 bits, while the ADC module of 28335 is 12 bits. Generally, it is mapped in peripheral frame 2 and left-aligned, so the first 4 bits are reserved, so it needs to be shifted right by 4 bits to get the actual value.

The ADC result registers are dual mapped. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait states and are left justified. Locations in Peripheral Frame 0 space (0x0B00-0x0B0F) are 1 wait state for CPU accesses and 0 wait state for DMA accesses, right justified. During high speed/continuous conversion use of the ADC, use the 0 wait state locations for fast conversion of ADC results to user memory.

ADC_MIRROR in DSP2833x_Headers_nonBIOS.cmd
: origin = 0x000B00, length = 0x000010 /* ADC Results register mirror /
ADC : origin = 0x007100, length = 0x000020 / ADC registers */