TMS320VC33 FLASH online programming method

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TMS320VC33 FLASH online programming method [Copy link]

In the TI company's TMS320VC33 DSP application system, the method of online programming of the DSP external FLASH memory through the JTAG port is given, and the automatic loading and running after the DSP system is powered on is given.
Keywords: DSP JTAG FLASH memory online programming Bootload
FLASH memory is a high-density. Non-volatile electrically erasable memory with large storage capacity, easy to use, and suitable for low-power. High-performance systems. In high-speed DSP application systems, in order to give full play to the DSP performance, the user code needs to be loaded into the high-speed RAM memory for operation after power-on. The following introduces the burning method of the SST29LE020 type FLASH memory, and how to realize the bootstrap (Bootload) of the user program after the TMS320VC33 is powered on.
1 Features and operation of SST29LE020 SST29LE020
is a 256K×8FLASH produced by SST. It has a lifespan of more than 100,000 erases and writes. It is divided into 2048 pages, each page is 128 bytes, and the page write cycle is 5ms. If a data in a page needs to be changed, all data in this partition must be reloaded. (The SST29LE020 are 256K x8 CMOS Page-Write EEPROM manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29LE020 write with a single power supply. Internal Erase/Program is transparent to the user. The SST29LE020 conform to JEDEC standard pinouts for byte-wide memories.) FLASH supports software data protection function (Software Data Protection). When executing a three-byte DSP write instruction, the protection function will be automatically added. Any subsequent write operation must be accompanied by a three-byte DSP write instruction.
The read operation of SST29LE020 is consistent with the traditional EPROM read operation; when performing data programming operations, it supports three modes: internal timing (Internal Timer), data query (Data#Polling), and toggle bit (Toggle Bit) to test whether the internal programming operation is completed. The FLASH software erase instruction is a 6-byte load instruction. After the instruction is executed, the entire chip is erased after waiting for a maximum of 20ms, that is, each data bit of the FLASH is restored to the full FF state of 1 state.
The SST29LE020 software instruction sequence can be found in the data sheet of SST. Before FLASH programming, the FLASH needs to be erased, and the erase operation requires six bus cycles.
The process of FLASH page write operation when using the internal timing method.
2 Introduction to TMS320VC33
TMS320VC33 is a 32-bit floating-point digital signal processor of the TMS320C3X series launched by TI in the United States. It is a lower-priced DSP developed based on the TMS320C31 floating-point DSP. The product has high speed, low power consumption, and low cost. The TMS320VC33 has significant advantages such as easy development. The TMS320VC33 uses an internal 1.8V and an external 3.3V power supply, so its power consumption is about an order of magnitude lower than that of the original model TMS320C31, and it can support an operating rate of up to 150M/FLOPS. Its main features are as follows:
The CPU is a 32-bit high-performance CPU: it can perform 16/32b integer and 32/40b floating-point operations; it contains 8 extended precision registers; it has 2 address generators. 8 auxiliary registers and 2 auxiliary register arithmetic units (ARAU). The
on-chip memory is a 32-bit instruction word. 24-bit address line. 34K×32b (1.1Mb) dual static RAM.
The peripheral interface has a startup program loading function; it contains a 5-fold frequency phase-locked loop (PLL) clock generator; the on-chip memory can map peripherals, including a serial port. Two 32-bit timers and one DMA; with four internal decoding page selections, it can greatly simplify the interface between TMS320VC33 and I/O and memory.
3 TMS320VC33 program boot function
TMS320VC33 has two memory mapping modes, namely MP (Microprocessor Mode) mode and MC/BL (Microcomputer/Bootloader Mode) mode. The location of the interrupt vector is different in the two modes. The MC mode is commonly used. In this mode, the MCBL/MP pin is connected to a high level, and the internal ROM is mapped to between 000 and FFF. This ROM now contains a boot program (BootLoader) solidified by the device manufacturer. The boot program can load the DSP real-time running program and data from the external low-speed ROM or serial port into the high-speed RAM.
After the TMS320VC33 is reset, it will run the internally solidified boot program, which determines the loading mode by querying the four interrupt pins. These pins are low level effective, and the query order is INT3.INT0.INT1.INT2; when INT3 is effective, it is serial loading mode; when INT0 is effective, it is loaded from external address 0x001000 (BOOT1); when INT1 is effective, it is loaded from external address 0x400000 (BOOT2); when INT2 is effective, it is loaded from external address 0xfff000 (BOOT3).
TMS320VC33 has four fast page select signals for addressing external address space.
When using external memory to load data, the external memory data header location must contain the following information:
(1) External memory width (8/16/32 bits);
(2) The length of the program code block;
(3) The destination start address of the loaded data;
(4) The timing control parameters of memory access.
Between the header information is the user's program code, which is arranged in the order of low bit first and high bit last. After the program code, there must be an all-zero word, that is, 0x00000000, to indicate that the bootloader user program code has ended. After the boot is completed, the user program will be executed from the loaded destination address.
4 FLASH online programming method
The debugging of TMS320VC33 uses CC for C3x/4X (Code COmposer) integrated programming environment, and the user board is simulated through the JTAG header. The user code is first placed in the external RAM for debugging. After the debugging is successful, the user program code can be written into FLASH. The following introduces the online programming method under the parallel loading BOOT2 mode.
The connection between SST29LE020 and TMS320VC33 is relatively simple. The FLASH chip select CE pin is directly connected to the PAGE1 pin of TMS320VC33; the simplest way to handle the FLASH output enable OE pin is to use a jumper (when writing data to FLASH, connect it to a high level; normally, connect it to ground).
When debugging the user program, you need to make a CMD file according to the memory space allocation of the user board. Assume that the user's extended external RAM is 32bit, the starting address is 0x00c00000, and the length is 32K; the external FLASH starting address is 0x00400000 (using BOOT2 mode), and the length is 256K. The CMD file is as follows:
MEMORY
{
INTRAM1:origin=0x00800000,length=0x00008000
INTRAM2:origin=0x00809800,length=0x000007c1
VEC:origin=0x00809fc1,length=0x3f
EXTRAM:origin=0x00c00000,length=0x00008000/*32k*/
FLASH:origin=0x00400000,length=0x00040000/*256*/
}
SECTIONS
{/*User program code and initialization data are placed in external RAM*/
.vectors>VEC /*Interrupt vector address specified by VC33*/
.text :LOAD=EXTRAM
.cinit>EXTRAM
.data:RUN=EXTRAM
.bss:RUN=INTRAM2
.stack>INTRAM1
}
Step 1: After compiling under CC, load the user .OUT file, and the user program code is written into the EXRAM space.
Step 2: According to the BOOT format of TMS320VC33 and the user .MAP file generated by CC, find the program entry address. The entry address and length of each loading block, and write the FLASH burning file. The sample source program listing is as follows:
#define MEM_WIDE 0x00000008 /*Flash memory width*/
#define CG_REGISTER 0x000010c8 /*Global memory configuration parameters*/
#define ENTER_POINT 0x00c00064 /*Program code entry address*/
volatile int *flash_add=(volatile int *)0x400000;/*External Flash mapping address*/
#define BOOTORG 0xc00064 /*Program entry address in .MAP file
#define BOOTBLK 3/*Number of load blocks in .MAP file*/
#define BOOTSRC1_ADD 0x00809fc1 /*The first load block address*/
volatile int *bootblk1_add=(volatile int *)0x00809fc1;
#define BOOTBLK1_LEN 0x3a /*length of the first load block*/
#define BOOTSRC2_ADD 0x00C00000 /*address of the second load block*/
volatile int *bootblk2_add=(volatile int *)0x00c00000;
#define BOOTBLAK2_LEN 0xa3 /*length of the second load block*/
#define BOOTSRC3_ADD 0x00C000a3 /*address of the third load block*/
volatile int *bootblk3_add=(volatile int *)0x00c000a3;
#define BOOTBLK3_LEN 0x17 /*length of the third load block*/
//////////////////////////////////////////////////
unsigned int flashaddnum,bytenum;
/*Define Flash address and page byte number variables*/
void waite(int ms)/****Software 1ms subroutine****/
{…………；}
void sdp_flash()/******Software data protection subroutine*********/
{flash_add[0x5555]=0xaa;/*3-byte chip SDP instruction*/
flash_add[0x2aaa]=0x55;
flash_add[0x5555]=0xa0;
}
void era_flash()/******Erase chip subroutine************/
{flash_add[0x5555]=0xaa;/*6-byte chip erase instruction*/
flash_add[0x2aaa]=0x55;
flash_add[0x5555]=0x80;
flash_add[0x5555]=0xaa;
flash_add[0x2aaa]=0x55;
flash_add[0x5555]=0x10;
waite(20); /*20ms wait for chip erase to complete*/
}
void write_flash(int bootdata)/***Write an int data***/
{unsigned int i;
for(i=0;i<3;i++) /*Write an int data into four bytes*/
{if(bytenum==0) /*If it is the first byte of the page, write the SDP instruction first*/
{sdp_flash();}
flash_add[flashaddnum]=bootdata; /*Write a byte to the Flash address*/
flashaddnum++; /*Flash address plus 1*/
bytenum++; /*Page byte plus 1*/
if(bytenum>127) /*After writing a page, set the page byte to 0 and wait for 11ms*/
{bytenum=0;wait(11);}
bootdata>>=8; /*Right shift the data to be written by 8 bits*/
}
}
void main() /***Main program***/
{unsigned int i,j,lenth;
bytenum=0;flashaddnum=0; /*Set the Flash address and page byte number*/
waite(1); /*Wait for 1ms*/
era_flash(); /*Erase Flash chip*/
write_flash(MEM_WIDE); /*Write external Flash memory width*/
write_flash(CG_REGISTER); /*Write register configuration parameters*/
write_flash(1); /*The data length of the first boot is 1*/
write_flash()ENTER_POINT; /*Write the destination address of the boot*/
write_flash(0); /*The first boot data*/
for(i=0;i<BOOTBLK;i++) /*Write the data blocks that need boot*/
{if(i==0) /*The first 2 bytes of each data block are the length and source address*/
{lenth=BOOTBLK1_LEN;
write_flash(BOOTHBLK1_LEN);
write_flash(BOOTSRC1_ADD);}
else if(i==1)
{lenth=BOOTBLK2_LEN;write_flash(BOOTBLK2_LEN);
write_flash(BOOTSRC3_ADD);}
else{;}
for(j=0;j<lenth;j++) /*Write the data block content to Flash*/
{if(i==0){write_flashbootblk1_add[j]};}
else if(i==1){write_flash(bootblk2_add[j]);}
else if(i==2){write_flash(bootblk3_add[j]);}
else{;}
}
}
write_flash(0); /*Write all zeros at the end of the code*/
write(10); /*Wait 10ms to ensure that the Flash writing is completed*/
}
Step 3: Modify. CMD file SECTION segment, link the burning program to the internal RAM area. . The SECTION segment in the CMD file is as follows:
SECTIONS
{/*Flash burning code and initialization data are placed in TMS320VC33 internal RAM*/
.text:LOAD=INTRAM1
.bss:RUN=INTRAM1
.cinit>INTRAM1
.stack>INTRAM1
}
Step 4: Run the burning program, the user code is written into the FLASH, connect the FLASH OE pin jumper to the position, use CC to check whether the FLASH memory content is consistent with the internal to be burned, and check it offline.
The FLASH online programming method has been verified on the user board and achieved the expected purpose. By using the JTAG emulator to program the external FLASH of the TMS320VC33 user system online, you can save the HEX conversion tool and EPROM programmer and other tools, and it is convenient and easy to use. This method of on-site online programming can be extended to other series of DSP user systems, and it is a new technology that needs to be mastered in DSP development.

kebi612

I would like to ask an expert a question. Can the chip with the suffix 150 or 120 be replaced with one without the suffix?

Also, this chip itself cannot store programs. It must be programmed with an external memory, right?