TPS563209 output voltage noise optimization and testing based on 500MHz bandwidth

Jacktang

TPS563209 output voltage noise optimization and testing based on 500MHz bandwidth [Copy link]

Low-power DCDC chips and their application circuits have been widely used in industrial and consumer electronic products. Since the filter circuits and decoupling capacitors in the system give the system a certain ability to resist high-frequency ripple interference, the bandwidth limit of the oscilloscope is usually selected to be 20MHz when measuring the output voltage ripple of DCDC. However, in some high-precision measurement systems and RF application systems, high-frequency ripples will bring a series of interference problems to the system. Therefore, in order to verify whether the DCDC output voltage ripple meets the system's restrictions on high-frequency ripples, the oscilloscope bandwidth limit will be selected to be 500MHz when measuring voltage ripples, which is called the output voltage noise test of DCDC. Since high-frequency signals are easily coupled through parasitic parameters, the design of DCDC circuits poses a great challenge. The following three aspects are used to effectively suppress the high-frequency components in the DCDC output voltage ripple, including PCB layout optimization, input and output decoupling capacitor design, and oscilloscope measurement method optimization. This article takes TPS563209 as an example for detailed discussion and experimental verification.

PCB layout optimization

Figure 1 is the schematic diagram of TPS563209EVM-652 . In this power circuit, the core power loop includes input capacitors, high-side and low-side MOSFETs built into the chip, power inductors and output capacitors. Therefore, in the process of PCB layout, minimizing the routing distance of the power loop and increasing the routing width of the power loop can effectively reduce the parasitic parameters of the power loop, thereby effectively reducing the high-frequency noise generated when the TPS563209 is working.

查看详情

Figure 1. Schematic diagram of TPS563209EVM-652

Figure 2 is the recommended TPS563209 PCB layout. All devices are on the same layer. GND directly connects the input capacitor ground, chip ground and output capacitor ground through the bottom of the chip. The loop of input capacitor, chip, inductor and output capacitor is minimal. There are 100nF decoupling capacitors at both input and output. Since switching noise is generated from inside the switching circuit, the input decoupling capacitor is close to the chip VIN pin, and the output decoupling capacitor is close to the last output capacitor. The voltage sampling point is the positive end of the output decoupling capacitor.

查看详情查看详情

Figure 2 TPS563209 recommended PCB Layout

Input and output decoupling capacitor design

Figure 3 is the frequency response curve of ceramic capacitors.

At low frequencies, the capacitive reactance of the capacitor plays a dominant role, so the equivalent impedance decreases as the frequency increases. At high frequencies, the inductive reactance of the capacitor plays a dominant role, so the equivalent impedance increases as the frequency increases.

Capacitors with different capacitance values have different response curves to frequency, as shown in Figure 3. Among the three types of ceramic capacitors, the 10uF/16V capacitor has the largest capacitance, so the equivalent impedance is lower at low frequencies. Therefore, it is suitable for use as an energy storage capacitor in switching power supply design. For example, uF-level ceramic capacitors are placed at the input and output of TPS563209 .

The capacitance of 100nF/25V capacitor is in the middle. The equivalent impedance curve in Figure 3 shows that the turning frequency is 28MHz. The equivalent impedance in the MHz frequency range is low. When testing the DCDC output voltage noise, the oscilloscope bandwidth is 500MHz, so the nF capacitor has a better filtering effect on the DCDC output noise. In this test, 100nF/25V ceramic capacitors are selected as decoupling capacitors.

The 100pF/50V capacitor has the smallest capacitance. The equivalent impedance curve in Figure 3 shows that the turning frequency is 1GHz, so the 100pF capacitor has a better filtering effect on high-frequency signals. Generally, pF-level capacitors are more commonly used in high-frequency communications.

Figure 3 Frequency response curve of ceramic capacitor

Oscilloscope measurement method optimization

In the test of output voltage ripple, engineers usually choose the test method shown in the left figure of Figure 4, where they weld metal probes to the signal line and ground line of the coaxial line, and then press the two metal probes to the positive and negative ends of the output decoupling capacitor. In this test method, the contact point between the metal probe and the capacitor is not reliable, which can easily introduce high-frequency noise. However, in the test of output voltage ripple, the oscilloscope bandwidth is usually set to 20MHz, and the high-frequency noise can be effectively filtered out, so no high-frequency noise can be observed from the signal waveform displayed by the oscilloscope.

However, in the output voltage noise test, the oscilloscope bandwidth is set to 500MHz, and the high-frequency noise is not effectively filtered out, but is directly displayed in the signal waveform of the oscilloscope. Therefore, in the output voltage noise test, the coaxial line needs to be carefully processed, as shown in Figure 5, the distance between the ground line and the signal line is as small as possible to reduce the coupling loop of the high-frequency noise. Then the coaxial line is soldered to the 100nF decoupling capacitor, as shown in the right figure in Figure 4.

查看详情

Figure 4 Output voltage noise test method

查看详情

Figure 5 Testing coaxial line

Experimental Results

Experimental conditions:

DCDC converter: TPS563209

Input voltage: 12V

Output voltage and current: 1V/3A

Figure 6 shows the test result based on poor PCB layout and incorrect test method, showing the output voltage noise is 310mV.

Figure 7 shows the test results based on a good PCB layout and an incorrect test method, showing an output voltage noise of 140mV.

Figure 8 shows the test result based on good PCB layout and correct test method, showing the output voltage noise is 34mV.

From the experimental results, it can be seen that a good PCB layout and correct testing methods are crucial to the testing of output voltage noise.

查看详情

Figure 6 Bad PCB layout and Bad test method

查看详情

Figure 7 Good PCB layout and Bad test method

查看详情

Figure 8 Good PCB layout and Good test method

in conclusion

The TPS563209 is a high-performance DCDC converter that can meet the stringent requirements on output voltage noise.

In order to obtain lower TPS563209 output voltage noise, the following three points need to be noted in DCDC design and output voltage noise measurement.

1. Good PCB layout.
2. Suitable decoupling capacitor selection.
3. Reasonable testing method.

References

1. TPS563209EVM-652 3-A, SWIFT Regulator Evaluation Module, SLVUAB2

alan000345

Picture 3 is missing. There is no picture 3.