Structural Design of Virtual I2C Bus Software Package Based on TMS320F206

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Structural Design of Virtual I2C Bus Software Package Based on TMS320F206 [Copy link]

Digital signal processors are increasingly used in various fields, among which TI (Texas Instrument)'s TMS320 series chips have taken a leading position. TMS320F206 (F206 for short) is favored in the development of mid-to-high-end instruments because it has 32K words of Flash on the chip, supports simulation debugging of the JTAG scan port, and supports serial download of programs, which is convenient for development and design and product software upgrades. Although
　　TMS320F206 has a high processing speed, it directly supports fewer I/O lines and has relatively weak control capabilities. Therefore, it is more suitable to use a serial interface with external devices. Commonly used serial interfaces and serial buses include UART and I2C bus. Since I2C bus provides a more complete bus protocol and the interface circuit is simple, it is widely used. At present, many peripheral devices support I2C interface, but most MCUs do not directly support I2C bus, so the method of using I/O line to simulate I2C has become a general solution. However, due to the complexity of I2C bus protocol and the particularity of operation management, it still causes great inconvenience to the development of such methods. Fortunately, a virtual I2C bus software package designed according to the platform mode and suitable for 80C51 is proposed in the literature, which greatly simplifies the I2C interface program design of 80C51, so that users can implement the corresponding interface without knowing the details of the I2C bus protocol. The literature also provides a software package for MSP430 microcontroller. Since there is no such software package for DSP, in order to simplify the design of such I2C interface program for DSP, this paper refers to the design principles in the literature and designs a software package suitable for the development of TMS320C2XX series DSP.
　　1 Design of virtual I2C software package
　　According to the best inclusive design, post-normalization design, and pre-normalization design principles mentioned in the literature, the software package is defined as follows.
　　(1) Scope of application
　　① Applicable to master transmission and master reception modes. The I2C bus has four working modes: master transmission, master reception, slave transmission, and slave reception. Since the actual DSP mostly works in the master mode of the I2C bus, the software package is designed for the master mode.
　　② It is applicable to the interface between TMS320C2XX series and I2C bus peripheral devices, supports reading and writing N bytes of peripheral devices, and the communication mode is point-to-point reading and writing after addressing the virtual node.
　　③ The simulated I/O port line can select any two of the four general I/O port lines (I/O0~I/O4).
　　(2) Software package structure design
　　TMS320C2XX series products basically include four general I/O port lines I/O0~I/O4 (since XF can only be used as an input port line and BIO can only be used as an output port line, they are not considered for the time being). Their input and output directions are set by the lower 4 bits of ASPCR, and the setting or reading of the corresponding port line status is controlled by the IOSR register. However, the DSP here is different from the 80C51. The input and output status of the port line is not automatically switched, and the ASPCR and IOSR registers do not support bit addressing. Therefore, it is more cumbersome to simulate the I2C bus working mode. In order to avoid changes in other status bits of the registers used, more AND and OR operations are required to change the status of the specified I/O port line. Therefore, the structure of this software package is slightly different from that of the 80C51 virtual I2C software package. Of course, these are all completed within the software package, and users do not need to understand the specific details. The user interface is also simple and easy to use.
　　① Software package composition. In order to simulate the operation timing of the I2C bus, the software package includes 2 macro definitions and 12 sub-functions.
　　(a) Timing simulation subroutine
　　Sendb--sends the start flag and starts the I2C bus; senda--sends the confirmation flag;
　　Sendna--sends the non-confirmation flag; Sende--sends the end flag.
　　(b) Operation simulation subroutine
　　geta--receives the confirmation flag; sendd--sends 8-bit data;
　　getd--receives 1 byte of data.
　　(c) Data read and write subroutine
　　wrnbyte--writes N bytes; rdnbyte--reads N bytes.
　　(d) Other macros and sub-functions:
　　subsendd--set the state of the analog data line according to the flag bit C; toggleclk--switch the state of the analog clock line;
　　Xdelay--delay subroutine; Sdainm--configure the analog data line A as an input line;
　　sdaoutm--configure the analog data line as an output.
　　Because the operating frequency of the DSP is generally much higher than the operating frequency of the I2C bus, a dedicated delay subroutine is required here to reduce the frequency of the analog clock line. The source program given in this article is for the case when F206 uses a 40 MHz crystal oscillator. Users can adjust the delay time according to actual conditions.
　　② Software package symbol definition. The software package includes the following symbol definitions:
　　VSDA, VSCL--define the mask bits corresponding to the analog data line and the analog clock line respectively. Since the operation of the general I/O line in DSP cannot be realized through bit operation, it can only be defined by masking bits. For example, if IO3 is used to simulate the data line and IO2 is used to simulate the clock line, IO3 can be defined as 08h and IO2 as 04h;
　　RAM0--a temporary storage unit for data storage;
　　RIO--a storage unit for saving the current state of the I/O line;
　　SLA--a storage unit for saving the node address on the bus and determining the transmission direction;
　　NUMBYTE--a storage unit for the number of bytes to be sent or received;
　　MTD--send data buffer;
　　MRD--receive data buffer.
　　In the above symbols, RAM0, RIO, SLA, NUMBYTE are page addresses, which are related to the current page pointer DP content setting; MTD and MRD are absolute addresses, which are independent of DP content.
　　③ Resource occupation. Auxiliary registers AR0, AR1, AR2, AR6, ACC, ASPCR, IOSR and other resources are used.
　　④ Application interface. The software package uses wrnbyte and rdnbyte as the only export interface. The user only needs to correctly set the content of the corresponding storage unit and call the corresponding sub-function:
　　splk ＃SLAR/ SLAW, SLA; write the transmission node address and transmission direction
　　splk ＃N, NUMBYTE; write the number of bytes to be transmitted
　　; if output, set the output buffer content
　　call wrnbyte/rdnbyte
　　3 Application Examples
　　3.1 Introduction to device related functions
　　X1203 is a low-power CMOS real-time clock chip with clock/calendar circuit and two alarms. It provides dual-port clock and alarm registers, and can work accurately during read and write operations. Its operating voltage ranges from 2.5 to 6 V, and its operating current is less than 1uA. The clock uses a low-cost 32.768 kHz crystal input to record time in seconds, minutes, hours, days, weeks, months and years. It has an automatic correction function for leap years and automatically adjusts for months with less than 31 days. The interrupt pin can be activated at a specified time by setting the interrupt flag, meeting the needs of most users for timer programming. The pin structure of the chip is shown in Figure 1 (SOIC package).
　　Among them, SCL is the clock input terminal, and data is synchronously input into the device or output from the device with the clock signal. The input buffer on this pin is always activated. The SDA terminal is a bidirectional pin for serial data input and output; it has an open drain and can be wired "OR" with other open drain or open collector outputs; a pull-up resistor is required, and in conjunction with the SCL pin, a 400 kHz 2-wire I2C interface can be realized. VBack is the backup power input terminal, which is used to supply power to the device when VCC fails. It is the interrupt signal output terminal, and the alarm signal can be generated at this terminal at the specified time by setting the alarm register; the drain is open, and the low level is valid. X1 and X2 are the input and output terminals of the inverting amplifier respectively; a 32.768 kHz square wave reference can be connected to the X1 terminal, or a 32.768 kHz quartz crystal can be connected to the X1 and X2 terminals to configure it as an on-chip oscillator. The clock starts counting only when at least one byte is written to the RTC register after the initial power-on.
　　The clock/control register (CCR) in X1203 is divided into 5 parts: 2 8-byte alarm registers (Alarm0, Alarm1), 1 1-byte control register, 1 8-byte real-time clock register and 1 1-byte status register. The alarm register can be used to set the time when the alarm occurs, and the control register can enable or disable the output of the alarm interrupt signal. The real-time clock register stores seconds, minutes, hours, days, weeks, months and years in BCD code, and the status register stores the alarm status flag bit and the read-write enable status bit. The status register setting determines whether the data can be written successfully. This register is listed in Table 1.
　　BAT identifies whether the device is currently working with VBack or VCC. AL1 and AL0 identify whether Alarm0 and Alarm1 match the real-time clock. RTCF indicates whether the real-time clock fails. This position is set to 1 after the main power fails. RWEL is the register write enable latch. 0 means prohibition. This position must be set to 1 before any writing of the clock/control register. WEL is the write enable latch. Low means prohibition. By writing 1 to this bit and writing 0 to other bits, this position can be set; by writing 0 to this bit and writing 0 to other bits, this bit can be cleared to 0. Only by setting RWEL and WEL in the specified order can CCR be successfully written.
　　At present, many DSP chips do not directly support the I2C interface, and F206 is no exception. Therefore, two general I/O port lines are used here to simulate the I2C interface. The interface between F206 and X1203 adopts the interface scheme shown in Figure 2.
　　Connect a 32.768 kHz quartz crystal to the X1 and X2 terminals, and configure the clock source as an on-chip oscillator. Connect VCC and VBACK through a diode and a resistor, and add a 0.47 F large capacitor to the ground. In this way, when the power fails or the system power is turned off, the large capacitor at the VBACK terminal can still be used to supply power to maintain the normal operation of the clock chip. The interface between it and F206 uses three lines. Here, IO2 is used to simulate the clock signal for communication, and IO3 is used as the data input and output line. The end can be determined according to user needs. If the clock chip needs to generate an interrupt, this end can be connected to the interrupt line of F206. Note that the SDA end and the end are open-drain, and a pull-up resistor must be added, otherwise normal communication cannot be achieved.
　　3.2 Read and write operations of X1203
　　Here only the basic process of F206 reading and writing X1203 is given, as shown in Figures 3 and 4, which are the reading and writing processes of the clock chip respectively. When writing registers, it is necessary to pay attention to whether the settings of WEL and RWEL in the SR register are correct, that is, first set WEL to be valid, and then set WEL and RWEL to 1, otherwise the data will not be written correctly. After writing, WEL and RWEL should be set to invalid to avoid erroneous operation.
　　Structural design of DSP virtual I2C bus software package
　　It should also be pointed out that after the system is powered on for the first time (after VBack and VCC are both invalid), the system will start working when at least one byte is written to the RTC register. In actual use, it should first be determined whether the RTCF bit in SR is 1. If so, it means that the system is used for the first time or VBack and VCC are both invalid. X1203 must be written at least once to make it count normally.