How is JTAG used for chip testing?

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How is JTAG used for chip testing?　 [Copy link]

The most important component used is the boundary scan chain . It is named boundary scan chain because it is located on the boundary of the processor. We know that the CPU communicates with the periphery through pins, and all data is input or output through pins. JTAG achieves the purpose of chip testing by monitoring the signal of the pin . The boundary scan chain is a component on the pin. As shown below:

Boundary Scan Chain Location

Through the boundary scan chain, when there is a signal input, the boundary scan chain can obtain the signal , and when the CPU wants to output a signal, the boundary scan chain can also obtain the signal to be output. In addition, the boundary scan chain can also be used to directly output signals to the outside.

Whether it is capturing or outputting signals, an interface is needed to save these signals. TDI and TDO are used to do this. As shown in the figure:

JTAG TDI TDO schematic

Originally, the boundary scan chain stores the signal on the pin. When our own signal is input through the TDI pin, a shift operation will occur along the direction of the red line above , that is,

TDI -> Boundary Scan Chain -> TDO , so we can get the signal on the boundary scan chain from TDO, and the signal we input from TDI will also go to the boundary scan chain.

The data on the pins that the CPU uses to communicate with the outside world are nothing more than instructions and data signals (including addresses and data). However, the combination of the two forms a complete program, and being able to monitor them means that we can debug the program. Generally, chips provide several independent boundary scan chains, and the control of the boundary scan chains is mainly completed through the TAP (Test Access Port) Controller .