Testing methods and diagnostic analysis for DSP-containing circuit boards

Aguilera

Testing methods and diagnostic analysis for DSP-containing circuit boards [Copy link]

In modern radar systems, DSP-containing circuit boards are widely used. DSP-containing circuit boards are usually based on a certain DSP chip as the core, and are equipped with dual-port RAM (DRAM) and flash memory (Flash) and other devices on the periphery. Most DSP chips support the IEEE1149.1 standard, and a boundary scan chain is formed in the circuit board to support boundary scan. This paper combines boundary scan technology with traditional external input vector test methods to provide a reference method for testing and diagnosis of DSP-containing circuit boards.
　　2. Introduction to circuit principles and overall test ideas
　　2.1 Introduction to circuit principles
　　This paper introduces the test method using a DSP-containing circuit board in a radar system as an example. The circuit is based on AD's ADSP-21160M as the core, plus DRAM, Flash, and signal matching converters. Flash provides configuration programs for DSP work. The four DSPs exchange data through the Link port. At the same time, some data lines and address lines of the DSP are connected to the data lines and address lines of the DRAM. The Link port of the DSP exchanges data with the external connector through a signal matching converter. The circuit board uses highly integrated devices in the circuit device composition. The chip packaging uses a variety of surface-mount devices such as PQFP132 and PLCC100. The device pin spacing is extremely small, and the use of probe pen testing may damage the circuit process; and the DSP chip on the circuit cannot be removed from the circuit board, so it is more reasonable to use boundary scan technology. As shown in Figure 1.
　　

　　2.2 Test and Diagnosis Analysis
　　Data analysis of the core device DSP in the circuit shows that the chip has a JTAG test interface and is capable of boundary scan testing. However, boundary scan testing is not based on IP core testing. Boundary scan technology can test circuits but cannot achieve comprehensive testing and diagnosis. Therefore, the circuit interconnection and device function testing can be achieved by combining with the traditional external input vector test method to achieve the purpose of fault location.
　　2.3 Test System Composition
　　Based on the test and diagnosis requirements, test tools and the characteristics of the circuit itself, the voltage stabilization circuit, JTAG test interface conversion circuit and a chip (FPGA) with boundary scan function are designed to realize the resources required for circuit testing.
　　* Voltage stabilization circuit. The voltage stabilization circuit filters and stabilizes the voltage sent by the programmable power supply of the test system to provide the working voltage of the board under test, ensuring that the power supply of the board under test will not mutate due to unexpected reasons.
　　* FPGA circuit. This part of the circuit provides the test address and data signals for the board under test. During the test, the JTAG port of the test link of the DSP on the board under test and the JTAG port of the FPGA on the adapter board are used to form a test link, realizing the interconnection test between the four DSPs, the connection test between the DSP and the connector, and the interconnection test between the FPGA and the DSP through the FPGA configuration program.
　　*JTAG test interface adapter circuit. The JTAG interface of the DSP on the board under test and the FPGA on the test adapter board form a test channel to form a boundary scan test link. As shown in Figure 2.

　　3. Test and diagnosis process development
　　The main contents of the test diagnosis process development based on boundary scan technology include the design of the edge scan device link, the setting of pin mapping relationship, the setting of boundary scan controller related documents, and the development of test script language. Figure 3 is the test diagnosis flow chart of the circuit board.
　　

　　*Test link function test. Test the connection of the test link composed of edge scan devices, and complete the test of whether the input and output functions of the edge scan device pins are normal. Only after the test link test passes can the boundary scan controller be used for subsequent testing.
　　*Interconnection test. According to the netlist file of the circuit schematic diagram of the board under test and the test adapter board schematic diagram, the boundary scan test software is used to test whether the interconnection lines between the five devices, the edge scan device (DSP) on the tested circuit board and the FPGA on the test adapter board, are open, short, or poorly soldered.
　　*Flash test. The control enable signal of each Flash on the tested circuit board is controlled by different devices. During the test of Flash, it is necessary to develop test scripts for each Flash test and diagnosis. During the test, the fault analysis and location are completed. The developed test script can locate the specific pin fault of the device.
　　*DRAM test. The trigger signal of the DRAM configuration program is sent through the connector, and the FPGA generates the read and write timing of the DRAM to test the read and write functions of the DRAM. The test results of the FPGA read and write are interpreted and certain test result data is generated. The connector collects the data to the test system to determine whether the function of this part of the circuit is normal.
　　The fault coverage of the test diagnosis process implemented according to the above development process is ≥83%, the fault detection rate is about 92%, and the fault isolation rate within 3 devices is ≥95%.
　　4. Summary
　　By placing a chip with boundary scan function on the test adapter board and forming a test cluster with the edge scan chip on the board under test, the traditional external input vector test makes up for the shortcomings of the edge scan test, thereby achieving a higher circuit test coverage.