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RISC-V is a typical three-operand, load-store RISC architecture, including three basic instruction sets and six extended instruction sets, as shown in Table 1, where RV32E is a subset of RV32I and is not counted separately.
The RV32I instruction set has only 47 instructions, but it can meet the basic requirements of modern operating systems. The 47 instructions can be divided into the following categories according to their functions.
(1) Integer operation instructions: implement arithmetic, logical, comparison and other operations.
(2) Branch transfer instructions: implement operations such as conditional transfer and unconditional transfer, and have no delay slot.
(3) Load and store instructions: implement byte, half-word, and word loading and storage operations, all using register relative addressing.
(4) Control and status register access instructions: implement atomic read-write, atomic read-modify, and atomic read-clear operations on system control and status registers.
(5) System call instructions: implement system call, debugging and other functions.
Instruction Format
Let's take a look at the instruction format first. This format is so regular that my obsessive-compulsive disorder disappeared instantly. Regular instruction encoding is not only comfortable for people with obsessive-compulsive disorder, but also for the processor. The more regular the instruction, the fewer gates the decoder needs, the smaller the chip area, and the faster the running speed.
No immediate subtraction?
If there is only addi but no subi, how to do subtraction? Whether in mathematics or programming, x - y is equivalent to x + (-y), which means that subtraction can be turned into addition. Converting the minuend to a negative number and then adding the subtrahend will achieve the same function as subtraction. Based on this principle, RISC-V only provides immediate number addition, not immediate number subtraction. If immediate number subtraction is required, the compiler must be asked to convert the immediate number into a negative number and then continue to use addition. This is probably why RISC-V treats immediate numbers as signed numbers.
x0 Simplified instruction set
By introducing the x0 register, many special instructions can be solved by using ordinary instructions plus x0 as operands. The number of instructions is greatly reduced. If the number of instructions is reduced, the decoding circuit of the processor will be simplified.
32-bit constants
Previously, when using ARM processors, ARM would store constants that could not be represented by immediate numbers in the constant pool, and then load them into registers using PC-related LDR instructions. RISC-V constants are completely spliced with instructions, and no Load instruction is required. You should know that using Load instructions requires additional access cycles. A single RISC-V instruction can represent a 12-bit signed constant, and more than 12 bits require two instructions to synthesize. One of the instructions is lui, and the lui instruction loads the upper 20 bits of the constant. The lower 12 bits can be added using the addi instruction. Of course, this process requires the compiler to carefully calculate what the immediate number is, because the addi instruction performs signed addition, and the 12-bit immediate number will be sign-extended to a 32-bit signed number before participating in the calculation. ARM constant loading requires 8 bytes, one instruction + one constant; RISC-V constant loading also requires 8 bytes, two instructions. The program space occupied is the same.
Only less than and greater than or equal to
RISC-V only has blt and bge for comparison jump instructions, that is, only less than and greater than or equal to. Are greater than and less than or equal to no longer needed? Yes, they are needed, but RISC-V uses a very clever method. By swapping the two operands involved in the comparison of blt, we get bgt, and by swapping the two operands involved in the comparison of bge, we get ble. What a good idea. Two instructions are used to achieve the work of four instructions, two of which are pseudo-instructions, and there are only two actual instructions.
Let the compiler do more
My understanding of RISC is: the processor should do as little as possible, and let the compiler do as much as possible. This makes sense, after all, the number of compilations is far less than the number of executions. The above paragraphs mentioned a lot of extra work for the compiler to do. Here is another example of the extra work that the compiler should do in order to simplify the design of the processor.
B-type is the format of jump instruction, J-type is the format of long jump or function call instruction. Pay attention to the order of their immediate values. I feel a little sorry for the compiler designer. How can this be done? To be more specific, the linker should be responsible for filling in the immediate values here. The purpose of arranging the offset address immediate values in this way is to simplify the design of the processor, but it obviously adds more work to the compiler.
Other omitted instructions
Many commonly used instructions are also omitted, such as nop, move, not, neg, of course, it does not mean that these functions do not exist, all of these functions are available, but they are equivalently implemented by other instructions, such as the not instruction is implemented by xori rd, rs, -1. Every time I see such instructions, I admire the great god of Berkeley.
Summarize
All instructions that can be saved are saved. All instructions that can be saved are done by the compiler. Absolutely streamlined.
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