MSP430Fr6972--AD usage summary

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MSP430Fr6972--AD usage summary [Copy link]

#include<msp430.h>

int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT

// GPIO Setup
P1OUT &= ~(BIT4 |BIT5); // Clear LED to start
P1DIR |= (BIT4 | BIT5); // P1.4/5 output

//1. Sampling pin configuration
/// Configured as AD function, P1.0~3 (A0~3) and P9.4~7 (A12~15) can be reused as AD sampling function
P1SEL1 |= BIT3;
P1SEL0 |= BIT3; /// Configure P1.3 for ADC：

// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;

//2.参考电压配置
// By default, REFMSTR=1 => REFCTL is used to configure the internal reference
while(REFCTL0 & REFGENBUSY); // If ref generator busy, WAIT
REFCTL0 |= REFVSEL_1 | REFON; // Select internal ref = 2.0V
// Internal Reference ON
//详见《user's guide》24.3.1

///3.ADC related register configuration
// Configure ADC12
//ADC12CTL0~2 control registersADC12CTL0
= ADC12SHT0_2 | ADC12ON; // Sampling and holding time 16ADCCLK; Enable AD (when ADC12ENC=0, modify to enable or disable AD)
ADC12CTL1 = ADC12SHP; // ADCCLK = MODOSC; sampling timer: Get signal from sample and hold
ADC12CTL2 |= ADC12RES_2; // 12-bit conversion results resolution
ADC12CTL3 |=ADC12CSTARTADD_5; // Select ADC12MCTL5 to control
ADC12IER0 |= ADC12IE5; // Enable ADC conv complete interrupt(ADC12MEM5)

///
...





|=ADC12CSTARTADD_5; //Select ADC12MCTL5 to control ADC12MEM5 to save AD conversion results
//ADC12IER0 |= ADC12IE5; Interrupt and response register correspondence
//Note: ADC12MEM0~31 and AD have 32 independent sampling channels A0~A31, and there is no need to use one-to-one correspondence
//In this example, channel A3 uses ADC12MEM5, that is, ADC12MEMx can be arbitrarily assigned to different channels, see Figure 25-1 for details
////////////////////////////////////////////////////////////////////////////////////
ADC12MCTL5 |= ADC12INCH_3 | ADC12VRSEL_1; //ADC12INCH_3 : Channel 3 //// ADC12VRSEL_1: internal reference voltage

//4. Wait for reference voltage configuration to complete
while(!(REFCTL0 & REFGENRDY)); // Wait for reference generator to settle

while(1)
{
//5.Ad sampling and obtaining results Note: AD sampling requires time, plus delay
__delay_cycles(5000); // Delay between conversions
ADC12CTL0 |= ADC12ENC | ADC12SC; // Sampling and conversion start

__bis_SR_register(LPM0_bits + GIE); // LPM0, ADC10_ISR will force exit
__no_operation(); // For debug only
}
}

///中断处理函数
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch (__even_in_range(ADC12IV, ADC12IV_ADC12RDYIFG))
{
case ADC12IV_NONE: break; // Vector 0: No interrupt
case ADC12IV_ADC12OVIFG: break; // Vector 2: ADC12MEMx Overflow
case ADC12IV_ADC12TOVIFG: break; // Vector 4: Conversion time overflow
case ADC12IV_ADC12HIIFG: break; // Vector 6: ADC12BHI
case ADC12IV_ADC12LOIFG: break; // Vector 8: ADC12BLO
case ADC12IV_ADC12INIFG: break; // Vector 10: ADC12BIN
case ADC12IV_ADC12IFG0: // Vector 12: ADC12MEM0 Interrupt
case ADC12IV_ADC12IFG1: break; // Vector 14: ADC12MEM1
case ADC12IV_ADC12IFG2: break; // Vector 16: ADC12MEM2
case ADC12IV_ADC12IFG3: break;
case ADC12IV_ADC12IFG4: break; // Vector 20: ADC12MEM4

///使用哪个ADC12MEMx存储AD结果，转换完成后就会触发响应寄存器的完成中断，标注位为ADC12IV_ADC12IFGx
///前提：ADC12IER0 |= ADC12IE5; //设置AD完成中断
case ADC12IV_ADC12IFG5: //break; // Vector 22: ADC12MEM5
if (ADC12MEM5 >= 0x6B4) // ADC12MEM = A1 > 0.5V?
P1OUT |= BIT5; // P1.4 = 1
else
P1OUT &= ~BIT5; // P1.4 = 0
__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU
break; // Clear CPUOFF bit from 0(SR)
case ADC12IV_ADC12IFG6: break; // Vector 24: ADC12MEM6
case ADC12IV_ADC12IFG7: break; // Vector 26: ADC12MEM7
case ADC12IV_ADC12IFG8: break; // Vector 28: ADC12MEM8
case ADC12IV_ADC12IFG9: break; // Vector 30: ADC12MEM9
case ADC12IV_ADC12IFG10: break; // Vector 32: ADC12MEM10
case ADC12IV_ADC12IFG11: break; // Vector 34: ADC12MEM11
case ADC12IV_ADC12IFG12: break; // Vector 36: ADC12MEM12
case ADC12IV_ADC12IFG13: break; // Vector 38: ADC12MEM13
case ADC12IV_ADC12IFG14: break; // Vector 40: ADC12MEM14
case ADC12IV_ADC12IFG15: break; // Vector 42: ADC12MEM15
case ADC12IV_ADC12IFG16: break; // Vector 44: ADC12MEM16
case ADC12IV_ADC12IFG17: break; // Vector 46: ADC12MEM17
case ADC12IV_ADC12IFG18: break; // Vector 48: ADC12MEM18
case ADC12IV_ADC12IFG19: break; // Vector 50: ADC12MEM19
case ADC12IV_ADC12IFG20: break; // Vector 52: ADC12MEM20
case ADC12IV_ADC12IFG21: break; // Vector 54: ADC12MEM21
case ADC12IV_ADC12IFG22: break; // Vector 56: ADC12MEM22
case ADC12IV_ADC12IFG23: break; // Vector 58: ADC12MEM23
case ADC12IV_ADC12IFG24: break; // Vector 60: ADC12MEM24
case ADC12IV_ADC12IFG25: break; // Vector 62: ADC12MEM25
case ADC12IV_ADC12IFG26: break; // Vector 64: ADC12MEM26
case ADC12IV_ADC12IFG27: break; // Vector 66: ADC12MEM27
case ADC12IV_ADC12IFG28: break; // Vector 68: ADC12MEM28
case ADC12IV_ADC12IFG29: break; // Vector 70: ADC12MEM29
case ADC12IV_ADC12IFG30: break; // Vector 72: ADC12MEM30
case ADC12IV_ADC12IFG31: break; // Vector 74: ADC12MEM31
case ADC12IV_ADC12RDYIFG: break; // Vector 76: ADC12RDY
default: break;
}
}