TMS320C66x Universal Parallel Port Software Reset

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TMS320C66x Universal Parallel Port Software Reset [Copy link]

Software Reset
A software reset clears the uPP internal state machine but does not reset the contents of the UPP registers. The following procedure performs a software reset of the UPP peripheral.
Step 2-2:
1. Write the EN bit in the uPP Peripheral Control Register (UPPCR) to 0 (disables the uPP).
2. Check the DB bit in the UPPCR for active; wait until the DMA controller is inactive/idle.
3. Write the SWRST bit in the UPPCR to 1 (places the UPP software reset).
4. Write the SWRST bit in the UPPCR to 0 (brings the UPP software reset).
2.7.2 Hardware Reset
When the processor reset pin is asserted, the entire processor is reset and remains in reset until the RESET pin is released. As part of the device reset, the UPP state machine is reset and the UPP registers are forced to their default states (see Section 3).
2.8 Interrupt Support
The UPP peripheral generates eight interrupt events, all dependent on the internal DMA channels I and Q. The UPP peripheral automatically groups all interrupt events into a single chip-level interrupt. Individual events may be enabled using the UPP Interrupt Enable Set Register (UPIES) and disabled using the UPP Interrupt Enable Clear Register (UPIEC). Only enabled events generate interrupts and assert bits in the Interrupt Enable Status Register (UPIER). Disabled events do not generate interrupts, but do assert bits in the Interrupt Raw Status Register (UPISR).
An interrupt service routine (ISR) can be assigned to handle interrupts using the UPP chip-level interrupt controller module. A single CPU interrupt (and a single call in the ISR) can represent multiple interrupt events if UPP events occur close to each other. Therefore, a UPP ISR must meet certain structural requirements:
The ISR must be able to handle multiple events before returning.
The ISR must handle subsequent events after the event that called it but before it returns.
The ISR must write 00h to the UPP End of Interrupt Register (UPEOI) before returning. This enables subsequent UPP events to generate CPU interrupts.