I want to use FPGA to make an SPI Slave. I have a few questions about the clock.

zengxy3407

I want to use FPGA to make an SPI Slave. I have a few questions about the clock. [Copy link]

Hi, everyone.

As a novice, I want to use FPGA to implement an SPI Slave. I searched online for other people's implementation methods. I have two confusions. Please give me some advice:

1. Is it better to use the external SCLK edge directly for data shifting or to use the SCLK edge after system clock synchronization? Or what are the advantages and disadvantages of each?

2. In one process, the state of a certain quantity is determined at the rising edge of the system clock, and in another process, the state of the quantity is changed at the rising edge of the system clock. Will this cause contention? For example, this code:

    -- -------------------------------------------------------------------------

    --  SPI CLOCK REGISTER

    -- -------------------------------------------------------------------------



    -- The SPI clock register is necessary for clock edge detection.

    spi_clk_reg_p : process (CLK)

    begin

        if (rising_edge(CLK)) then

            if (RST = '1') then

                spi_clk_reg <= '0';

            else

                spi_clk_reg <= SCLK;

            end if;

        end if;

    end process;



    -- -------------------------------------------------------------------------

    --  SPI CLOCK EDGES FLAGS

    -- -------------------------------------------------------------------------



    -- Falling edge is detect when SCLK=0 and spi_clk_reg=1.

    spi_clk_fedge_en <= not SCLK and spi_clk_reg;

    -- Rising edge is detect when SCLK=1 and spi_clk_reg=0.

    spi_clk_redge_en <= SCLK and not spi_clk_reg;

CLK is the system clock, and its spi_clk_reg is latched on the rising edge of CLK, so the obtained spi_clk_fedge_en and spi_clk_redge_en should also be aligned with the rising edge of CLK. However, when shifting data, the rising edge of CLK is also used:

    -- -------------------------------------------------------------------------

    --  RECEIVED BITS COUNTER

    -- -------------------------------------------------------------------------



    -- The counter counts received bits from the master. Counter is enabled when

    -- falling edge of SPI clock is detected and not asserted CS_N.

    bit_cnt_p : process (CLK)

    begin

        if (rising_edge(CLK)) then

            if (RST = '1') then

                bit_cnt <= (others => '0');

            elsif (spi_clk_fedge_en = '1' and CS_N = '0') then

                if (bit_cnt_max = '1') then

                    bit_cnt <= (others => '0');

                else

                    bit_cnt <= bit_cnt + 1;

                end if;

            end if;

        end if;

    end process;

That is to say, at the same time as the rising edge of CLK, spi_clk_fedge_en needs to be changed and the state of spi_clk_fedge_en needs to be judged. Isn't this approach prone to competition?

Please give me more advice.

Source code: https://github.com/jakubcabal/spi-fpga

heningbo

Here is a sample program showing how to write SPI. I hope it can help you.

heningbo

In fact, most people don’t like to help others look at code, because they have to read the code according to your ideas, which is a waste of time.

zengxy3407

heningbo posted on 2019-7-5 22:41 In fact, most people don’t like to help others read the code, because they have to read the code according to your ideas, which is a waste of time.

Makes sense! Put the question first

tom.hu

If you use an external clock directly, it is not conducive to pipeline construction, but the upper limit of the frequency that can be achieved will be higher than that of using the internal clock sampling method. If the frequency is not high, the subsequent design will be more flexible after using oversampling synchronization.