Summary of configuring 5409's McBSP as an SPI port

fish001

Summary of configuring 5409's McBSP as an SPI port [Copy link]

Finally I figured out the configuration of the McBSP of 5409! Now I will write down what I did, so that people who come after me can avoid detours in this regard. My goal is to configure the MCBSP as an SPI compatible interface. I use MCBSP0. Below I give the initialization program of the McBSP I wrote in assembly. It has been debugged, but there may be some mistakes. Please correct me after reading it! .include "cpu_reg.inc" .def McBsp0Init McBsp0Init: stm #spcr10,spsa0 ;Receive reset stm #0000h,spsd0 stm #sp cr20,spsa0 stm #0000h,spsd0 ;Send reset rpt #9 nop STM #spcr10,spsa0 STM #1800h,spsd0 ;clkstp=11b *---------------------------PCR0------------------------------------ stm #pcr0,spsa0 ;CLKXP=0,CLKXM=1,FSXM=1,FSXP=1 ;xx..............;RESERVED ;..0.............;When XIOEN=0, DS, FSX, CLKX are configured as serial interface ;...0............;When RIOEN=0, DR, FSR, CLKR, CLKS are configured as serial interface pins ;....1...........;When FSXM=1, the frame synchronization mode bit of the sampling rate generator (FSGM bit of SRGR2) determines the frame synchronization signal ;.....0..........;FSRM＝1, the on-chip sampling rate generator generates a frame synchronization signal, and FSR is an output pin (unless GSYNC of SRGR＝1) ;......1.........;In SPI mode, when CLKXM＝1, McBSP is the master device and generates a clock (CLKX) ; to drive its receive clock (CLKR) and the SCLK clock of the system's SPI slave device ;.......1........;When DLB=0, ;CLKRM=0, the receiving clock is driven by the external clock ;CLKRM=1, the receiving clock is driven by the internal sampling rate generator ;When DLB=1, ;CLKRM=0,The receive clock is driven by the transmit clock. The characteristics of CLKX are set by the CLKXM bit of the PCR. The CLKR pin is in high impedance state. CLKRM=1, CLKR is an output pin driven by the transmit clock (CLKX). The characteristics of CLKX are set by the CLKXM bit of the PCR. ........x.......;RESERVED, CLKS pin status bit. When CLKS is selected as a general-purpose input, this bit reflects the value of the CLKX pin ;..........x.....;DX pin status bit ;...........x....;DR pin status bit ;............1...;Frame synchronization pulse FSX is valid at low level ;.............0..;Frame synchronization pulse FSR is valid at low level ;..............0.;Transmit clock polarity, when CLKXP＝0, transmit data is sampled on the rising edge of CLKX ;...............0;Receive clock polarity, when CLKRP＝0, transmit data is sampled on the rising edge of CLKR stm #0b08h,spsd0 *-------------------SRGR20----------------------------------- stm #srgr20,spsa0 ;0...............;GSYNC=0, sample rate generator register clock (CLKG) free running ;.0..............;CLKSP=0, generate CLKG and FSG on the rising edge of CLKS ;..1.............;CLKSM=1, sample rate generator clock is driven by CPU clock ;...0............;FSGM=0, transmit frame synchronization signal (FSX) is generated when DXR is copied to XSR ;When FSGM=0, FPER and FWID are ignored ;....xxxxxxxxxxxx;FPER,frame period stm #2000h,spsd0 ;clksm=1,fsgm=0 *--------------------SRGR10---------------------------------- stm #srgr10,spsa0 ;DSP clock is 60MHz,MBF200 is 12MHz ;xxxxxxxx........;FWID,frame width ;........00110000;CLKDV=48,sampling rate generation clock divider stm #0030h,spsd0 ;clkgdv=30h, SPI clock=DSP clock/48 ;=1MHz [size =4] nop nop *----------------------RCR10--- ------------------------------- stm #rcr10,spsa0 ;x.............;RESERVED ;.0000000..... ...;RFLEN1=0000000, 1 word per frame ;.....100....;RWDLEN1=100, 24 bits per word ;...........xxxxx;RESERVED stm #0080h,spsd0 *----------- ----------RCR20------------------------------------ [/size ] stm #rcr20,spsa0 ;0...............;RPHASE=0 , single-phase frame ;.0000000........;RFLEN2=0000000, 1 word per frame [size=4 ] ;........100.....;RWDLEN2=100, 24 bits per word ;...... .....00...; RCOMPAND=00, no extension, data transmission starts from the highest bit (msb) ;.............0..;RFIG=0, the first received frame synchronization pulse restarts data transmission [ /size] ;..............01;RDATDLY=01, delay one bit of data stm #0081h,spsd0 ;rdatdly= 01 *-------------------------XCR10------------- --------------------- stm #xcr10,spsa0 ; send ;x...............;reserved ;.0000000........;XFRLEN1=0000000, every Frame 1 word ;..........100....;XWDLEN1=100, 24bit per word ;..........XXXXX ;RESERVED stm #0080h,spsd0 ; *----------------------- --XCR20---------------------------------- stm #xcr20,spsa0 ;Send ;0.............;XPHASE=0,single-phase frame ; .0000000..........;XFLEN2=0000000,1 word per frame ;........100.....;XWDLEN2=100,24bit per word ;...........00...;XCOMPAND=00,no extension,data transmission starts from the highest bit (MSB) ;.............0..;SFIG=0,restart data transmission after the first frame synchronization pulse ;..............01;XDATDLY=01,delay one bit of data stm #0081h,spsd0 *-----------------------SPCR20---------------------------------------- STM #spcr20,spsa0 STM #0040h,spsd0 ;grst=1 rpt #9 nop ;wait *---------------------------SPCR10--------------------------------------- stm #spcr10,spsa0 ;RINTM=10 ;0...............;DLB=0,forbid loop return ;.00.............;RJUST=00,DRR is right-aligned, high-order 0 is added ;...11...........;CLSTP=11,clock stop mode, with delay ;.....xxx........;RESERVED ;........0.......;DXENA=0,DX enable off ;.........0......;ABIS=0,disable ABIS mode ;..........10....;RINTM=10,receive interrupt RINT is generated by a new frame synchronization signal ;............0...;RSYNCERR＝0,no receive synchronization error ;.............0..;RFULL=0,RBR does not overflow ;..............0.;RRDY＝0,receiver is not ready ;...............1;RRST=1,open serial port reception stm #9821h, spsd0 rpt #9 nop *----------------------------------SPCR20---------------------------------- stm #spcr20,spsa0 ;xxxxxx...;RESERVED ;...0... ;.....0....;FRST=0,The frame synchronization logic circuit is reset. The sampling rate generator will not generate the frame synchronization signal FSG ;.........1......;GRST=1, the sampling rate generator exits from reset. CLKG generates a clock signal according to the programmed value in the sampling rate generator register (SRGR); ..........10....;XINTM=10, the transmit interrupt XINT is generated by a new frame synchronization signal; .............0...;XSYNCERR=0, no transmit frame frame synchronization error; .............0..;XEMPTY=0, XSR is empty; ..............0.;XRDY=0, transmitter is not ready; ..............1;XRST=1, open the serial port to send; stm #0061h,spsd0; rpt #9 nop stm #spcr20,spsa0 ;FRST=1 orm #0080h,spsd0 rpt #6 nop ret