Design of frequency sweeper using digital frequency synthesis technology, FPGA and single chip microcomputer

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Design of frequency sweeper using digital frequency synthesis technology, FPGA and single chip microcomputer [Copy link]

The frequency characteristics of a network include amplitude-frequency characteristics and phase-frequency characteristics. When designing a system, the frequency characteristics of each network have an important impact on the stability, working frequency band, transmission characteristics, etc. of the system. In actual operation, the sweep frequency meter greatly simplifies the measurement operation, improves work efficiency, and achieves the purpose of fast, intuitive, accurate and convenient measurement process. It is widely used in production, scientific research and teaching. This design uses digital frequency synthesis technology to generate sweep frequency signals, with single-chip microcomputer and FPGA as the control core, and realizes the step adjustment of the sweep frequency signal frequency, digital display and display of the amplitude-frequency characteristics and phase-frequency characteristics parameters of the measured network through interface circuits such as A/D and D/A converters. 1 System Overall Scheme and Design Block Diagram 1.1 System Overall Scheme Take the sine swept frequency signal source with adjustable output frequency step as the excitation Vi of the network under test, and the response of the network under test can be obtained as V0. By measuring the amplitude of each frequency point, the effective value of V0 and Vi can be obtained, and the ratio of the two is the amplitude frequency response of the point; V0 and Vi are compared and shaped by zero crossing, and then sent to FPGA to measure the phase difference, the phase-frequency characteristic can be obtained. The output v*(n) of the input g*(n) is the complex conjugate of v(n). So we get the expression of output y(n): Design of frequency sweeper using digital frequency synthesis technology, FPGA and single-chip microcomputer Therefore, the output signal and the input signal are sine waves with the same frequency, with only two differences: 1 The amplitude is weighted, that is, the amplitude function value of the network system at ω=ω0; 2 The phase of the output signal is equivalent to the input having a q(ω0) delay, that is, the phase value of the network system at ω=ω0. The control of amplitude and phase measurement of this scheme is realized by FPGA, which can make the measurement results accurate. 1.2 System overall design block diagram The system obtains the external set frequency sweep range and frequency step through keyboard scanning, and controls DAC904 by calling the DDS control module to output the frequency sweep signal. Since the signal will be greatly attenuated in the stop band of the network under test, the sweep signal of the network under test is processed by program-controlled amplification, and then the effective value is sampled by AD637 and shaped by LM311. The effective value of the signal is converted into a digital value by MAXl270, and the shaped signal is processed by the phase measurement module to obtain the phase difference value. Two RAMs are written into the FPGA to store the effective value and phase difference value of the measured signal. After completing a frequency sweep, the amplitude-frequency and phase-frequency curves are displayed on the oscilloscope through the waveform display module, and the amplitude and phase difference values of specific frequency points are displayed on the LCD. The system implementation block diagram is shown in Figure 1. Design of frequency sweeper using digital frequency synthesis technology, FPGA and single-chip microcomputer 2 Design of system function part 2.1 Generation of frequency sweep signal Direct digital synthesis (DDFS) signal source. It is a completely digital method: first, the digital quantity of the discrete sample amplitude of a cycle of sine wave (or other waveform) is pre-stored in ROM or RAM, and read out at a certain address increment interval. After D/A conversion, it becomes an analog sine wave signal waveform of different frequencies, and then the burrs are filtered out by low-pass to obtain the input signal of the required frequency. According to this principle, DDS can synthesize any waveform, and can accurately control the phase, and the frequency is also very stable. It is quite easy to make using FPGA, and the frequency sweep step is simple to implement. Assume that the frequency of the reference frequency source inside the FPGA is fclk, a phase accumulator with a counting capacity of 2N (N is the number of bits of the phase accumulator), and a frequency control word of M, then the frequency of the DDS system output signal fout=fclk／2N×M. The frequency resolution is: △f=fclk／2N. If the crystal frequency is selected as 40 MHz, the frequency control word is 24 bits, and the number of bits of the phase accumulator is 31 bits, then the output frequency range is 0.02 Hz～312 kHz, and the step frequency is 40 MHz／231≈0.02 Hz. The system uses a high-speed 14-bit current output D/A converter DAC904 to make a DDS sweep signal source. The FPGA is fed with a 20 MHz clock signal to output a 10 Hz～100 kHz sweep signal. The PCB board made of this device takes grounding into consideration well, so that the output signal can reach no obvious distortion at a frequency of 1 MHz. DAC904 adopts internal reference and bipolar connection, and the output signal amplitude range is 0-5 V. Its schematic diagram is shown in Figure 2.

2.2 Amplitude-frequency characteristic test plan Use the integrated true RMS converter AD637 to first detect the effective value of each frequency point of the signal, and then read the obtained data into the microcontroller for processing after A/D sampling. The device has a simple external circuit and a wide working frequency band. When cascaded with an A/D converter, it can sample the effective value, average value, mean square value, and absolute value of any complex waveform. The measurement error is less than ± (0.2% reading + 0.5 mV), which can achieve high measurement accuracy. 2.3 Phase-frequency characteristic test scheme The counting method is used to measure the phase. The idea of the counting method is to convert the phase quantity into a digital pulse quantity, and then measure the digital pulse to obtain the phase difference. The converted digital pulse quantity is XORed to generate another square wave with a pulse width of T0 and a period of T. If the high-frequency counting clock pulse period is TCP, the count value within a period of T is: 398171 In the formula, φx is the degree of the phase difference. This method is widely used, has high precision, simple circuit form, and is suitable for FPGA implementation. In actual measurement, when the frequency of the two input signals is high and the phase difference is small, the pulse obtained is very narrow, which will cause a large error. In order to overcome the above defects, the idea of equal precision measurement is introduced (as shown in Figure 3), and the multi-cycle synchronous counting method is adopted. The trigger is used to generate a gate signal with a width that is an integer multiple of the measured signal fa. Counter 1 is used to measure the number N1 of high-frequency pulses fm passing through the gate signal, and counter 2 is used to measure the number N2 of pulses after the gate signal, XOR signal, and high-frequency pulse are ANDed in the same time. Therefore, the phase difference value is △φ=N2／N1x360°. While measuring the phase, a D flip-flop is introduced inside the FPGA, and one square wave signal is used to control another square wave. The high and low output of the flip-flop is used to determine whether the signal phase difference range is greater than 180° or less than 180°.

2.4 System display circuit design In order to display the curve on the oscilloscope, it is necessary to send the scanning signal and data signal to the X and Y axes synchronously through two D/A converters. The DA converter in the X-axis direction outputs a scanning signal of 0~5 V sawtooth wave signal, and the data signal is -5~5 V, which reflects the signal amplitude and phase at each frequency point, and is output to the Y-axis direction by another D/A converter. 3 System software design The system software design consists of a single-chip microcomputer and FPGA. The entire system takes the user key interrupt as the main line, calls different processing functions, and exchanges data with each control module in the FPGA through the bus, realizing the function of measuring the frequency characteristics of the system. The software flow chart is shown in Figure 4.

4 Conclusion This frequency sweeper uses digital frequency synthesis technology (DDS) to generate sweep signals. Through the 14-bit D/A converter DAC904, a 10 Hz to 100 kHz sine sweep signal is generated and applied to the network under test. The network output signal is measured through the effective value sampling circuit and the phase measurement circuit implemented by the comparator LM311 and the FPGA. In order to test the performance of the system, a resistor-capacitor double-T network with a center frequency of 5 kHz and a bandwidth of ±50 Hz was made. The test results show that in the passband and stopband of the network, the phase-frequency characteristic measurement has achieved a measurement accuracy of less than 3°, and the measurement error of the amplitude-frequency characteristic is less than 50%. In addition, the system can input the frequency sweep range through the keyboard, display the amplitude-frequency and phase-frequency curves through the oscilloscope, and display the amplitude and phase characteristic values of the network at a specific frequency point on the LCD. The system is simple to operate, low cost, accurate in measurement, and has strong practicality.