FPGA error, added clock timing, and how to solve this error

chuzhaonan

FPGA error, added clock timing, and how to solve this error [Copy link]

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)
        Critical Warning (332169): From sys_clk (Rise) to sys_clk (Rise) (hold)

coyoo

Which device? Xilinx or Altera?

浦利丰

Have you tried adjusting the parameters?

testset

The original poster of A should provide the tool version code. Personally, I think it is not a problem with xdc, but a problem with the code.

lcl_woniu

Is this a simulation issue?