MSP430 clock setting and application summary

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MSP430 clock setting and application summary [Copy link]

********************************Based on MSP430F1612******************************* In MSP430 microcontroller, one clock cycle = the inverse of the MCLK crystal oscillator. If MCLK is 8MHz, then one clock cycle is 1/8us. One machine cycle = one clock cycle, that is, each action of 430 can complete a basic operation. One instruction cycle = 1~6 machine cycles, depending on the specific instruction. In addition, the instruction length is just a storage unit and has no necessary relationship with time. The clock module of MSP430 microcontroller mainly includes: Three clocks: auxiliary clock ACLK, main clock MCLK, subsystem clock SMCLK Three oscillators: low-frequency clock source LFXT1, high-frequency clock source XT2, digital control RC oscillator DCO The clock required for the operation of MSP430 microcontroller is generated by these oscillators after oscillation and processing. (1)ACLK: obtained by dividing the LFXT1CLK signal by 1/2/4/8. It is mainly used as the clock of low-speed peripherals. (2)MCLK: determined by one of LFXT1CLK, XT2CLK, and DCOCLK. It is selected by software and then obtained by dividing by 1/2/4/8. It is mainly used for CPU and system. (3)SMCLK: can be determined by LFXT1CLK and DCOCLK, or XT2CLK and DCOCLK, and then obtained by dividing by 1/2/4/8. It is mainly used for high-speed peripheral modules. The clock module of MSP430 is determined by the five registers DCOCTL, BCSCTL1, BCSCTL2, IE1, and IFG1. The specific functions are as follows: DCOCTL: Control DCO oscillator BCSCTL1: Control XT2, LFXT1, DCO oscillation, and control ACLK frequency division BCSCTL2: Set the three clock sources to choose which oscillator We set the register in the program, that is, set the three oscillators. After the clock oscillator is set, we also need to set the clock module, that is, let the three clock modules MCLK SMCLK ACLK select the corresponding clock oscillator to get clocks of different frequencies. After the PUC signal, the system selects the internal resistor to achieve the frequency output. RSELx = 4 and DCOx = 3, so that the DCO has a moderate frequency at the beginning. The clock signals of MCLK and SMCLK all come from DCO, which is about 800KHz (chip manual). After the PUC signal, set LFXT1 to LF mode (XTS=0), turn off the HF mode (XTS=1) and turn off the XT2 oscillator. (1) DCOCTL: DCO control register, address 56H, initial value 60H // 7 6 5 4 3 2 1 0 // DCO2 DCO1 DCO0 MOD4 MOD3 MOD2 MOD1 MOD0 // // DCO0~DCO2: DCO Select Bit, defines one of 8 frequencies, and the frequency is defined by the current injected into the DC generator // MOD0~MOD4: Modulation Bit, frequency fine-tuning // // DCO setting: Set the DCO frequency by setting DCOCTL and BCSCTL1 // (1) DCO adjustment: Set the DCOR bit to select external or internal resistance to determine a reference frequency. Divide the frequency by RSELx in the BCSCTL1 register to determine the clock frequency; Select the frequency by coarse-tuning DCOx in the DCOCTL register based on the nominal frequency; Fine-tune the frequency by the value of MODx in the DCOCTL register to select a frequency between DCOx and DCOx+1 // Note: When the DCO operates at the highest frequency, the normal value of the internal resistance is about 200k, and the operating frequency of the DCO is about 5MHz. Example: //The initial value of DCOCTL is 60H, that is, DCOCTL |= DCO1 + DCO2; DCOCTL |= DCO0 + DCO1 + DCO2; // Max DCO //MOD0~MOD4: Modulation Bit, the fine-tuning of the frequency can generally be kept at the default value //By default, RSELx=4 (2)BCSCTL1(ACLK):Basic Clock System Control 1, the address is 58H, the initial value is 84H // 7 6 5 4 3 2 1 0 // XT2OFF XTS DIVA1 DIVA0 XT5V RSEL2 RSEL1 RSEL0 // // RSEL2~RSEL0: Select an internal resistor to determine the nominal frequency (0 is the lowest, 7 is the highest) // XT5V: 1, this bit is not used and must be reset // DIVA0~DIVA1: Select the division coefficient of ACLK. DIVA=0,1,2,3(DIVA_0,DIVA_1...),ACLK's division coefficients are: 1,2,4,8 // XTS: select LFXT1 to work in low frequency crystal mode (XTS=0) or high frequency crystal mode (XTS=1) // XT2OFF: control the opening (XT2OFF=0) and closing (XT2OFF=1) of XT2 oscillator // // BCSCTL1 setting: initial value is 84H //Use XT2 oscillator//control the opening (XT2OFF=0) and closing (XT2OFF=1) of XT2 oscillator BCSCTL1 &= ~XT2OFF;//clear OSCOFF/XT2 do { IFG1 &= ~OFIFG;//clear OFIFG OSC_Delay = 255; while(OSC_Delay --);//delay waiting } while(IFG1 & OFIFG); //Until OFIFG=0 //RSEL2~RSEL0: Select an internal resistor to determine the nominal frequency (0 is the lowest, 7 is the highest) BCSCTL1 |= RSEL0 + RSEL1 + RSEL2; // XT2on, max RSEL //Select the division coefficient of ACLK: DIVA=0,1,2,3, the division coefficients of ACLK are: 1,2,4,8 respectively //BCSCTL1 |= DIVA_2; //Divide ACLK by 2 //(3)BCSCTL2(SMCLK,MCLK):Basic Clock System Control 2, address is 58H, initial value is 00H // 7 6 5 4 3 2 1 0 // SELM1 SELM0 DIVM1 DIVM0 SELS DIVS1 DIVS0 DCOR // // DCOR:Enable External Resister, 0—Select internal resistor, 1—Select external resistor // DIVS0~DIVS1: DIVS=0,1,2,3, the corresponding SMCLK division factor is 1,2,4,8 // SELS: Select the clock source of SMCLK, 0: DCOCLK, 1: XT2CLK/LFXTCLK // DIVM0~DIVM1: Select the MCLK division factor, DIVM=0,1,2,3, the corresponding MCLK division factor is 1,2,4,8 // SELM0~SELM1: Select the MCLK clock source, 0,1: DCOCLK, 2: XT2CLK, 3:LFXT1CLK // // BCSCTL2 settings: initial value is 00H // Set BCSCTL2, select the clock source XT2 of MCLK and SMCLK, and set its frequency division factor // Note: ACLK can only come from LFXT1, and the frequency division of ACLK can be set in BCSCTL1, that is, the maximum value of ACLK can only be 32768Hz (XIN and XOUT are indirectly 32.768KHz crystal oscillator) // DCOR is generally set to the default value // Set the frequency division factor of SMCLK, DIVS0~DIVS1: DIVS=0,1,2,3, corresponding to the frequency division factor of SMCLK is 1,2,4,8 // BCSCTL2 = DIVS_0; // BCSCTL2 = DIVS_1; // BCSCTL2 = DIVS_2; // BCSCTL2 = DIVS_3; //Set the frequency division factor of MCLK, DIVM0~DIVM1: DIVM=0,1,2,3, the corresponding frequency division factor of MCLK is 1,2,4,8 //BCSCTL2 = DIVM_0; //BCSCTL2 = DIVM_1; //BCSCTL2 = DIVM_2; //BCSCTL2 = DIVM_3; //BCSCTL2: Set the three clock sources to select which oscillator //SELM0~SELM1: Select the clock source of MCLK, 0,1:DCOCLK, 2:XT2CLK, 3:LFXT1CLK //Select MCLK clock source as XT2, //BCSCTL2 = SELM_2 ; //SELS: Select the clock source of SMCLK, 0:DCOCLK, 1:XT2CLK/LFXTCLK //Select SMCLK clock source as XT2 //BCSCTL2 = SELS ; //Select MCLK and SMCLK as XT2 BCSCTL2 = SELM_2 + SELS; //(4)IE1,Interrupt Enable Register 1 // 7 6 5 4 3 2 1 0 // OFIE // 7~2 and 0 : These bits may be used by other modules // OFIE:Oscillator fault interrupt enable. 0---Interrupt not enabled // 1---Interrupt enabled //(5)IEG1,Interrupt Flag Register 1 // 7 6 5 4 3 2 1 0 // OFIFG // 7~2 and 0 : These bits may be used by other modules // OFIE:Oscillator fault interrupt flag. 0 No interrupt pending // 1 Interrupt pending // After the PUC signal, DCOCLK is used as the clock signal of MCLK and SMCLK by default. Since the initial value of DCOCTL is 60H, the clock source of MCLK can be set to LFXT1 or XT2 as needed. The setting order is as follows: //(1)Clear OSCOFF/XT2 //(2)Clear OFIFG //(3) Delay and wait for at least 50us //(4) Check OFIFG again. If it is still set, repeat steps (1) to (4) until OFIFG = 0 //(5) Set the corresponding SELM of BCSCTL20 No interrupt pending // 1 Interrupt pending // After the PUC signal, by default, DCOCLK is used as the clock signal for MCLK and SMCLK. Since the initial value of DCOCTL is 60H, the clock source of MCLK can be set to LFXT1 or XT2 as needed. The setting sequence is as follows: //(1) Clear OSCOFF/XT2 //(2) Clear OFIFG //(3) Delay and wait for at least 50us //(4) Check OFIFG again. If it is still set, repeat steps (1) to (4) until OFIFG=0 //(5) Set the corresponding SELM of BCSCTL20 No interrupt pending // 1 Interrupt pending // After the PUC signal, by default, DCOCLK is used as the clock signal for MCLK and SMCLK. Since the initial value of DCOCTL is 60H, the clock source of MCLK can be set to LFXT1 or XT2 as needed. The setting sequence is as follows: //(1) Clear OSCOFF/XT2 //(2) Clear OFIFG //(3) Delay and wait for at least 50us //(4) Check OFIFG again. If it is still set, repeat steps (1) to (4) until OFIFG=0 //(5) Set the corresponding SELM of BCSCTL2