DDR3 initialization failed

flying~

DDR3 initialization failed [Copy link]

 After initializing ddr, local_cal_fail is high. I found that the pll clock is not locked and pll_lock is always low. I used a function signal generator to generate a stable clock and connected it. The clock is locked, but the initialization still fails. I used signaltop to introduce ddr signal debugging and found that mem_rst_n has no signal. However, there is a signal in the official simulation. As shown in the figure, the yellow signal is pulled low and then set high before the initialization is successful. This signal is output by the ddr controller in the FPGA to ddr3. At present, it seems to be a problem with the controller. But there are really limited things that can be changed. Apart from the clock and reset, what else can I change? ? ? ? ? I can't see anything that can be changed in the IP parameters. Even if I change it, it shouldn't affect the reset. I feel hopeless: Sad: I saw on the Internet that the reset delay is 1000clk. I wonder, I use periodic reset, so there shouldn't be any problem.

yupc123

Are you using a hard core or a soft core? I have encountered this problem before. I used a hard core. At that time, I changed some parameters in the DDR3 IP, which allowed me to adjust it. You can also try to change it. This problem is usually caused by poor PCB wiring.

Adrianer

I also encountered this problem. However, when I mounted the DDR3-UNIPHY on the NIOS II system with the same parameters, the read and write tests were all OK, but the bare CORE logic call in the FPGA failed to initialize. In addition, there was another set of the same DDR3 on the ARM A9 side, which was also OK.

Adrianer

If it is not solved, you can try it with NIOS II in QSYS to confirm whether it is a circuit problem or an instantiation problem. If it is solved, can you share the problem?

chengxiuyuan

Hi, is the problem solved? I am facing the same problem as you.

chengxiuyuan

Hello, can I add your QQ? My problem has not been solved yet. My QQ is 570327113

chengxiuyuan

Hello, may I ask how you finally solved the problem of mem_rst_n always having no signal? I have been working on it for a long time and it has been stuck here. I hope you can give me some advice when you see it. Thank you very much.

flying~

No solution, no work done.