Periodic feedback pure digital phase-locked loop based on actel fpga

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Periodic feedback pure digital phase-locked loop based on actel fpga [Copy link]

A periodic feedback pure digital phase-locked loop based on actel FPGA: Simply put, it is to establish a state machine, update the value of the input cycle parameter at the first time of each cycle of the clock, and then enter the next state counting, and return to the initial state when the count is consistent with the input cycle. The code synthesis simulation is correct, and the process is relatively simple, so I will not teach you how to do it. If there are any inappropriate parts, let's learn and communicate together and improve them together. The code is as follows: //Top-level module: module TE_DPLL_B(sys_clk, sys_rst, clk_in, clk_out); //---Global parameters---parameter DATA_W = 16; // The cycle counter and data bit width are adjusted according to the difference between the system clock and the input clock. parameter PN_EDGE = 2'b01; // Edge detection parameter (01=rising edge, 10=falling edge) parameter DPLL_M = 2; // M parameter parameter DPLL_N = 10; // N parameter //---Input and output interface--- input sys_clk; // System clock input sys_rst; // System reset input clk_in; // Input clock output clk_out; // Output clock TE_DPLL_Figure TE_DPLL_Figure_0( .sys_clk(sys_clk), // System clock .sys_rst(sys_rst), // System reset .clk_i(clk_in), // Input clock .t_o(n_ti) // Input clock period value ); defparam TE_DPLL_Figure_0.CNT_W = DATA_W; // Period counter bit width defparam TE_DPLL_Figure_0.PN_EDGE = PN_EDGE; // Edge detection parameters (01=rising edge, 10=falling edge) //--------------------------------------------------------- // Instantiate feedback module //--------------------------------------------------------- TE_DPLL_Feed TE_DPLL_Feed_0( .sys_clk(sys_clk), // System clock .sys_rst(sys_rst), // System reset .ti_i(n_ti), // Input period value .clk_o(clk_out) // Output clock ); defparam TE_DPLL_Feed_0.DATA_W = DATA_W; // Data bit width defparam TE_DPLL_Feed_0.PN_EDGE = PN_EDGE; // Edge detection parameter (01=rising edge, 10=falling edge) defparam TE_DPLL_Feed_0.DPLL_M = DPLL_M; // M parameter defparam TE_DPLL_Feed_0.DPLL_N = DPLL_N; // N parameter endmodule

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//Periodic sampling modulemodule TE_DPLL_Figure( sys_clk, sys_rst, clk_i, t_o ); //---Global parameters--- parameter CNT_W = 16; // Period counter bit width parameter PN_EDGE = 2'b01; // Edge detection parameters (01=rising edge, 10=falling edge) //---Input and output interface--- input sys_clk; // System clock input sys_rst; // System reset input clk_i; // Input clock to be tested output t_o; // Output clock period reg [CNT_W-1:0] t_o; //---Internal register--- reg [1:0] n_edge; // Clock buffer to be tested, used to detect clock edge reg [CNT_W-1:0] n_cnt; // Period counter reg n_state; // State //--------------------------------------------------------- // 2D Left shift register, used to detect rising or falling edge //--------------------------------------------------------- always @(posedge sys_clk) begin if(sys_rst) n_edge <= 0; else n_edge <= {n_edge[0],clk_i}; end //--------------------------------------------------------- // 1 state machine //--------------------------------------------------------- always @(posedge sys_clk) begin if(sys_rst) begin n_state <= 0; n_cnt <= 0; t_o <= 0; end else case(n_state) 0 : begin n_state <= (n_edge == PN_EDGE) ? 1 : 0; // Detect positive edge (determined by PN_EDGE) n_cnt <= (n_edge == PN_EDGE) ? 1 : 0; end 1 : begin n_state <= (n_edge == PN_EDGE) ? 0 : 1; // When it is not a positive edge (determined by PN_EDGE), jump back to state 0 n_cnt <= n_cnt + 1; t_o <= (n_edge == PN_EDGE) ? n_cnt : t_o; end default : n_state <= 0; endcase end endmodule

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// Feedback modulemodule TE_DPLL_Feed( sys_clk, sys_rst, ti_i, clk_o ); //---Global parameters--- parameter DATA_W = 16; // Data bit width parameter PN_EDGE = 2'b01; // Edge detection parameter (01=rising edge, 10=falling edge) parameter DPLL_M = 10; // M parameter parameter DPLL_N = 10; // N parameter //---Input and output interface--- input sys_clk; // System clock input sys_rst; // System reset input [DATA_W-1:0] ti_i; // Input clock period value output clk_o; // Output clock //---Internal signal--- wire [DATA_W-1:0] n_to; // Output clock period value //---Internal register--- reg [DATA_W-1:0] n_terr; // Open-loop error, error value after dividing M reg [DATA_W-1:0] n_err; // Feedback error, input and output clock period error //--------------------------------------------------------- // Feedback error (To/N) // Feedback clock period multiplied by feedback gain 1/N //--------------------------------------------------------- always @(posedge sys_clk) begin if(sys_rst) n_err <= 0; else n_err <= ti_i - (n_to / DPLL_N); // Input clock period - (output clock period / N) end //--------------------------------------------------------- // Open-loop error (n_err/M) // Feedback error multiplied by open-loop gain 1/M //--------------------------------------------------------- always @(posedge sys_clk) begin if(sys_rst) n_terr <= 0; else n_terr <= n_err / DPLL_M; end //--------------------------------------------------------- // Feedback n_err/M value to the control object //--------------------------------------------------------- TE_DPLL_Gen TE_DPLL_Gen_0( .sys_clk(sys_clk), // system clock .sys_rst(sys_rst), // system reset .terr_i(n_terr), // error n_err divided by M .clk_o(clk_o) // output clock ); defparam TE_DPLL_Gen_0.DATA_W = DATA_W; // data bit width //--------------------------------------------------------- // Output clock period measurement module, samples the output clock and measures the output clock period To //--------------------------------------------------------- TE_DPLL_Figure TE_DPLL_Figure_1( .sys_clk(sys_clk), // system clock .sys_rst(sys_rst), // system reset .clk_i(clk_o), // output clock is fed back to the period measurement module .t_o(n_to) // output clock period ); defparam TE_DPLL_Figure_1.CNT_W = DATA_W; // cycle counter bit width defparam TE_DPLL_Figure_1.PN_EDGE = PN_EDGE; // edge detection parameter (01 = rising edge, 10 = falling edge) endmodule

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Timing simulation with the above code parameters:

fsyicheng

Not many people use this brand.

teleagle

fsyicheng posted on 2018-10-12 22:12 Not many people use this brand.

Pure code, has nothing to do with what device is used.