This reference design provides a practical example of using an interleaved RF sampling analog-to-digital converter (ADC) to achieve a 12.8-GSPS sampling rate. This is accomplished by time interleaving the two RF sampling ADCs. Interleaving requires phase shifting between ADCs, which this reference design achieves using the noiseless aperture delay adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize the mismatch typical of interleaved ADCs: maximizing SNR, ENOB and SFDR performance. This reference design also features a low phase noise clock tree supporting JESD204B, which is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.
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