【Updating】This is an 8bit CPU! WLN08_03

This is an 8bit CPU built with 74 chips! Named WLN08_03, the hardware resources include 32Byte ROM, 8Byte RAM, 8 instructions, classic five-level pipeline, Harvard architecture, adjustable main frequency, entry-level 8bit CPU, suitable for DIYers who want to understand the structure and operating principles of CPU.

The project is being updated. Each module is being tested and has not yet been finalized. Please do not make any boards (if you want to do your own research, you can also modify it by yourself). Please stay tuned and follow us for updates!

First, let’s briefly talk about the structure of the CPU: there are about 8 separate modules, connected through the databus bus, and the core core controls each module individually.

sys_tick : system clock generation module

alu : computing module

work_reg : work register

prog_rom : program memory

pc/ir : program counter, instruction register, etc.

core : the main core of the CPU, controlling the logic of each module

Other modules are to be added. . .

The working principle needs to be added. . .

WLN08_03 is a simplified version of the instruction set of WLN08_01. It is partially deleted in order to better reproduce it with an independent 74-bit chip. The early WLN08_01 can judge and jump (equivalent to if), but _03 does not have such advanced functions. Only sequential statements can be executed, without branch jumps and ALU comparisons.

WLN08_01 frame diagram:

PROG_RAM

Input: addr[3:0] address selection en: output enable databus[7:0] data output

Function: Store program data, read-only

Principle: Use an 8-bit DIP switch to store one byte. In order to maintain the habit of dialing up to 1 and dialing down to 0, the circuit is designed to output a high level when the byte address is selected, but 138 is the output. The low level is active, so 238 is selected. The top of the DIP switch is connected to the decoder output, and the bottom is connected together and 10K is pulled low to connect to the data output buffer. The address selection part consists of four 3-8 decoders to form a 5-32 decoder. The data output buffer selects 573. LE is always 1 and OE low-level output is valid.

work_reg

Input: addr[2:0] address selection cp: rising edge address latch en: low level output enable read: rising edge read data write: rising edge write data databus[7:0]: data bus

Principle: The working register is composed of 8 573s. The outputs of these 8 573s are all connected to the bus. The read and write part is implemented: first use a register to latch the address. Since the LE of the 573 is a high-level latch data, the OE is a low-level power. If the flat output is enabled, you can use 138 to control OE and 238 to control LE, and use the output enable of the decoder to control reading and writing respectively. Since the inputs and outputs of these eight 573s are connected to the bus, 138 and 238 must ensure that only one is working at the same time.

Read reg timing: addr address provides>cp rising edge latch address data>release databus>read enable

Write reg timing: addr address provides>cp rising edge latch address data>databus prepares data>write enable

PC: There is nothing to say about this. Two 161s form a hexadecimal counter, and it has a preset number function that can correspond to the jmp jump instruction, and the output is provided to the program memory PROG_RAM.

sys_tick: System clock module. The clock source has two selection methods: 555 and MCU. The frequency range is 1hz-10Khz. The frequency output by the clock source is divided into 4 sequential step clocks.

The T0-T3 waveform diagram is as shown:

ALU: The calculation module has four operation modes: addition, self-increment by one, self-decrement by one, and negation. The principle is self-understanding and will be explained later.

Current progress: Test the maximum speed and waveform of the SYS_TICK system clock - OK; test the PC counting logic timing - OK; verify the ALU function - OK; test the work_reg function - OK; verify prog_ram - OK.

The verification of each module is OK, and the core module is being designed.

You may not believe it when I tell you. I bought a fake chip from a certain store. The 573 chip was hot and the 02 pin was reversed, which caused the progress to be delayed. . .

That's right, I bought it from Uxin. I cleared mines here. To buy components, it's better to go to Lichuang Mall to buy genuine products (LCSC pays!).

CORE design:

Instruction set: Currently, the 10 instructions are designed as follows. Verilog is being written, and the circuit will be designed and implemented later.

Testing function:

Update slowly. . . . . .