This circuit is a flexible frequency agile IF to baseband receiver. Variable gains in the IF and baseband are used to adjust signal levels. The ADRF6510 baseband ADC driver also includes a programmable low-pass filter to eliminate out-of-channel blocking and noise.

The bandwidth of this filter can be dynamically adjusted as the input signal bandwidth changes. This ensures that the available dynamic range of the ADC driven by this circuit is fully used.

The core of the circuit is the IQ demodulator. The ADL5387 's 2×LO phase separation architecture supports wide frequency range operation. Precise quadrature balance and low output DC offset ensure minimal impact on error vector magnitude (EVM).

The interfaces between all components in this circuit are fully differential. If DC coupling is required between different stages, the bias levels of adjacent stages should be compatible with each other.

Receiver architecture

The direct conversion (also called homodyne or zero-IF) architecture of the receiver is described in this circuit note. In contrast to a superheterodyne receiver, which can perform multiple frequency conversions, a direct conversion radio can perform only one frequency conversion. The advantages of primary frequency conversion are as follows:

• Reduce receiver complexity and reduce the number of stages required; improve performance and reduce power consumption
• Avoids image rejection issues and unwanted mixing products; only requires one LPF at baseband
• High sensitivity (adjacent channel rejection ratio [ACRR])

Figure 1 shows the basic schematic of the system, consisting of a cascaded IF variable gain amplifier (VGA) with integrated automatic gain control (AGC) loop, followed by a quadrature demodulator with variable baseband gain. programmable low-pass filter. The components shown in gray in Figure 1 ( ADF4350 and AD9248 ) are for clarity and are not included in the system-level measurements (see the Common Variations section for details on these devices).

Ideally, the input of the first stage and the output of the last stage should set the dynamic range (signal-to-noise ratio) of the system. In reality, this may not be the case. Placing a cascaded VGA before the quadrature demodulator not only gives the system more gain, but also benefits the overall system noise performance, as long as the VGA has a lower noise figure than the quadrature demodulator, as long as the VGA still has gain, and is not Attenuation occurs. The noise figure of subsequent stages is divided by the gain of the initial VGA. Another advantage of providing a VGA (versus only a fixed gain amplifier) ​​is that the AGC loop can be designed to level the input signal to the quadrature demodulator. The ability to impose this limit on the signal levels of the quadrature demodulator and any subsequent stages is very important.

IF VGA and AGC loop

The IF VGA and AGC loop functions can be implemented through the ADL5336 . It features two cascadable VGAs, each with 24 dB of analog dynamic range, and the maximum gain on each VGA can be changed digitally via the SPI port.

To implement the signal leveling AGC function, each ADL5336VGA has a square-law detector connected to the output through a programmable attenuator. The detector compares the attenuator output to an internal reference voltage of 63 mV rms. If there is a difference between the attenuator output and the 63 mV rms reference voltage, an error current is generated and integrated into the CAGC capacitor. The AGC loop is closed by connecting the DTO1/DTO2 pins to the GAIN1/GAIN2 pins. In order for the AGC loop to operate properly, the MODE pin is pulled low, resulting in a negative VGA gain slope.

Each ADL5336VGA has an allowed input power range within which the AGC will be leveled to a specific set point. Outside this range, the VGA output increases or decreases in dB increments with the input (assuming the VGA is not in compression or the signal is not within the noise floor).

IQ demodulator

The signal is routed from the ADL5336 to the ADL5387 , where it is demodulated and frequency converted to zero-IF. The ADF4350 frequency synthesizer provides the required 2×LO signal to the ADL5387 (see the Common Variations section); however, the actual testing used the signal generator instead of the ADF4350.

The ADL5387 uses two double-balanced mixers, one for the I channel and one for the Q channel. The LO provided to the mixer is generated using a divide-by-2 quadrature phase splitter. This provides the 0° and 90° signals for the I and Q channels. The ADL5387 provides approximately 4.5 dB of conversion gain from the RF input to the baseband I and Q outputs.

Low-pass filter, baseband VGA and ADC driver

Low pass filtering, baseband gain and ADC driver functions are all used ADRF6510 to achieve. The signal applied to the ADRF6510 now has independent I and Q paths. The signal is first amplified through a preamplifier, then low-pass filtered to suppress any unwanted out-of-band signals and/or noise, and finally amplified through the VGA.

Each channel of ADRF6510 can be divided into three levels:

• Preamplifier
• Programmable low pass filter
• VGA and output drivers

The preamplifier has user-selectable gain of 6dB or 12dB via the GNSW pin. The low-pass filter is programmable via the SPI port to a corner frequency of 1MHz to 30MHz in 1MHz steps. VGA has a 50dB gain range and a gain slope of 30mV/dB. The VGA gain is controlled through the GAIN pin. When the GNSW pin is pulled low, the range can be from 0.5dB to +45dB. When the GNSW pin is pulled high, the range can be from +1dB to +51dB. The output drivers are capable of driving 1.5Vpp differential into a 1k load while maintaining above 60dBc for HD2 and HD3.

The maximum CW signal that can be applied to the low-pass filter while still maintaining acceptable HD levels within the ADRF6510 is 2Vpp. If there is a large out-of-band interferer that could overload the inputs of the ADL5387 and/or ADRF6510, the out-of-band interferer (and the required in-band signal) can be attenuated by the ADL5336VGA. Once the out-of-band interference source is suppressed by the ADRF6510's low-pass filter, the desired signal can be amplified using the XAMPVGA (filter immediately following the ADRF6510).

The IQ signal from the ADRF6510 can be applied to an appropriate analog-to-digital converter (ADC), such as the AD9248.

Measurement results

A 4-QAM, 5 MSPS modulated signal is applied to the input of the ADL5336. For more information on test setup, see the "Circuit Evaluation and Testing" section.

EVM is a measure of the performance quality of a digital transmitter or receiver, reflecting the deviation of actual constellation points from their ideal positions due to amplitude and phase errors. as shown in picture 2.

Figure 3 shows system EVM versus ADL5336 input power with the maximum gain on VGA set to 15.2dB for VGA1 and 19.5dB for VGA2.

Several AGC set point combinations were tested. Figure 4 is also the relationship between system EVM and ADL5336 input power; however, the VGA gains are set to 9.7dB and 13.4dB respectively. The same AGC set point combinations were tested.

Figures 3 and 4 illustrate that the signal level applied to the ADRF6510 must be kept low enough to avoid compressing the input stage and/or filter. At the highest AGC set points (500mVrms and 707mVrms), the input to the ADL5387IQ demodulator begins to compress and cause additional drops in EVM. Optimum EVM is achieved when the AGC set point is at its lowest point (88mVrms). When the set point is 250mVrms, EVM has started to decrease.

Figure 5 compares EVM between the minimum and maximum digital gain settings on the ADL5336VGA (VGA both set to gain code 11 or gain code 00), where the VGA1 and VGA2 set points are 250 mVrms and 88 mVrms, respectively.

For a given AGC setpoint, when the maximum gain code is 11, the switch from VGA2 to VGA1 occurs after VGA2 has exceeded the gain range; therefore, the signal level applied to the ADRF6510 continues to increase (while the EVM decreases) until VGA1 reaches set point. Once VGA1 reaches the set point, the EVM flattens out again; therefore the signal level applied to the ADRF6510 does not change at an input power of approximately 5 dBm unless VGA1 goes out of the gain range. When the maximum gain code is set to 00, both VGAs provide more attenuation, thus allowing the VGA2 to shift the dynamic range so as not to hit the set point with input power as low as when the maximum gain code is 11. This allows VGA2 to remain at set point at higher input power, allowing VGA2 to VGA1 switching to occur before VGA2 goes out of gain range. This ensures that the signal level applied to the ADRF6510 remains at a constant value until the highest point of the input power range is reached.

Figure 6 compares EVM between the minimum and maximum digital gain settings on the ADL5336 VGA (both VGAs set to gain code 11 or gain code 00); however, the VGA1 and VGA2 set points are 707mVrms and 88mVrms respectively.

The dynamics in Figure 6 are the same as Figure 5, but more exaggerated. When the maximum gain code is 00, VGA2 reaches the set point at approximately -40dBm input power. It maintains the set point to about -10dBm, at which point VGA1 has not yet reached the set point of 707mVrms. VGA1 will not reach set point unless the input power is about 0dBm and the EVM starts to flatten slightly. The same thing happens again when the maximum gain is set to 11; however, VGA2 only maintains the set point to about -20dBm because no more gain is available to obtain the specified set point.