The circuit shown in Figure 1 uses the AD5700 , the industry's lowest power and smallest HART ¹ -compatible IC modem, and the AD5420 , a 16-bit current output DAC, to form a complete HART-compatible 4 mA to 20 mA solution. Very common in loop powered transmitter applications.

To further save space, the AD5700-1 provides an internal oscillator with 0.5% accuracy.

The circuit complies with the HART physical layer specifications defined by the HART Communication Foundation, such as analog slew rate and silent period noise specifications.

For many years, 4 mA to 20 mA communications have been used in process control instrumentation. This communication method is stable and reliable, and has high immunity to environmental interference in long-distance communications. However, the limitation is that only one process variable can be communicated in one direction at a time.

The Highway Addressable Remote Transducers (HART) standard was developed to enable high-performance bidirectional digital communications while supporting the 4 mA to 20 mA analog signals used by traditional instrumentation equipment. It derives various features such as remote calibration, troubleshooting and transmission of additional process variables. Simply put, HART is a digital two-way communication system that modulates a 1 mA pp Frequency Shift Keying (FSK) signal on top of a 4 mA to 20 mA analog current signal.

Figure 1 shows how the AD5420 can be used with the AD5700 HART modem and UART interface to enable HART support for the 4 mA to 20 mA current outputs commonly used in PLC and DCS systems. The HART_OUT signal output from the AD5700 is attenuated and AC coupled to the R _SET pin of the AD5420. If an external R _SET resistor is not used, an alternative method of connecting the AD5420 and AD5700 is provided in application note AN-1065 , where the AD5700 HART modem output is coupled to the AD5420 through the CAP2 pin. The method described in this circuit note requires the use of an external RSET resistor and has higher power supply rejection than the alternative method of the application note. Regardless of which solution is used, the AD5700 HART modem output can modulate analog current from 4 mA to 20 mA without affecting the dc level of the current (as shown in Figure 2). The diode protection circuit (D1 − D4) is discussed in detail in the transient voltage protection section.

Determine external component values

C1 and C2 can be used with the digital slew rate control function of the device to control the slew rate of the IOUT signal corresponding to the AD5420. When determining the absolute value of the capacitor, ensure that the modem's FSK output passes without distortion. Therefore, the bandwidth of the modem output signal must pass the 1200 Hz and 2200 Hz frequencies. Figure 3 shows the circuit that implements this requirement. In this case C2 remains open circuit.

The low-pass and high-pass filter circuits are formed through the interaction of RH _, CL _, CH _, and C1 in conjunction with some internal circuitry of the AD5420. When calculating the values ​​for these components, target low-pass and high-pass frequency cutoff points of >10 kHz and <500 Hz, respectively. Figure 4 shows a plot of the simulated frequency response, and Table 1 shows the effect on the frequency response of increasing each component value while keeping the remaining component values ​​constant.

The output of the modem is an FSK signal including 1200 Hz and 2200 Hz frequency shifts. This signal needs to be converted into a 1 mA peak-to-peak current signal. To do this, the signal amplitude on the R _SET pin must be attenuated. This is because the AD5420 has an internal current gain configuration design. Assuming that the modem's output amplitude is 500 mV peak-to-peak, its output must be attenuated by a factor of 500/150 = 3.33. This attenuation is achieved through R _H and _CL .

The measurements in this circuit note were made using the following component values:

• C1 = 4.7 nF
• R _H = 27 kΩ
• C _L = 4.7 nF
• C _H = 8.2 nF

Figure 5 shows frequency shifts of 1200 Hz and 2200 Hz measured on a 500 Ω load resistor. Channel 1 shows the modulated HART signal coupled into the AD5420 output (set to output 4 mA), while Channel 2 shows the AD5700 TXD signal.

HART compatibility

To be compatible with HART, the circuit in Figure 1 must comply with the HART physical layer specification. The HART specification document contains many physical layer specifications. The two most important of these are output noise and analog change rate during silence.

Output noise during silence

When the HART device is not transmitting (quiet), there should be no noise coupled onto the network in the HART extended band. Excessive noise may interfere with the device itself or other devices on the network receiving HART signals.

The voltage noise measured at a 500 ¬ load contains no more than 2.2 mV rms of broadband noise and associated noise combined in the extended frequency band. This noise is measured by connecting an HCF_TOOL-31 filter (available from the HART Communications Foundation) across a 500 Ω load and connecting the filter output to a true rms meter (see Figure 6). You can also use an oscilloscope to check the peak-to-peak voltage of the output waveform.

AD5420 output current settings are 4 mA, 12 mA, and 20 mA. No significant difference in noise was measured. The measured rms values ​​were 115 μV rms and 252 μV rms with and without the HCF_TOOL-31 bandpass filter, respectively. Both values ​​are within the required 2.2 mV rms (with HART filter) and 138 mV rms (wideband noise without HART filter) specifications.

Figure 7 and Figure 8 show oscilloscope plots of 4 mA and 12 mA output current, respectively. Note that the filter has a passband gain of 10. Channel 1 and Channel 2 show the input and output of the filter respectively.

simulated rate of change

This specification ensures that the maximum rate of change of analog current does not interfere with HART communications when the device regulates current. Step changes in current can disrupt the HART signal. Still use the same test circuit shown in Figure 6. For this test, the AD5420 was programmed to output a periodic waveform switching from 4 mA to 20 mA with no delay at either value to obtain maximum rate of change. To comply with the HART specification, the peak voltage of the waveform at the filter output cannot be greater than 150 mV. Compliance with this requirement ensures that the maximum bandwidth of the analog signal is within the specified DC to 25 Hz frequency band.

The typical time for the AD5420 output to change from 4 mA to 20 mA is approximately 10 μs. This speed is obviously too fast and will cause significant damage to the HART network. In order to reduce the change rate, the AD5420 provides two features: one is to connect capacitors at the CAP1 and CAP2 pins, and the other is to provide digital slew rate control function (please refer to the AD5420 data sheet for details ).

To reduce the bandwidth below 25 Hz, very large capacitor values ​​are required at the CAP1 and CAP2 pins. The best solution is to combine an external capacitor with the AD5420's digital slew rate control feature. The purpose of the two capacitors, C1 and C2, is to reduce the rate of change of the analog signal; however, this is not sufficient to meet the specification. Enabling the slew rate control feature provides flexibility in setting the slew rate.

Figure 9 shows the output of the AD5420 and the output of the HART filter. The peak voltage at the filter output is 80 mV, which is within the specified range. The slew rate is set to SR CLOCK = 3 and SR STEP = 2, the transition time from 4 mA to 20 mA is set to approximately 120 ms, C1 = 4.7 nF, and C2 is not connected. If this rate of change is too slow, the slew time can be reduced. But this will increase the peak voltage at the filter output. A capacitor connected from CAP1 to AV _DD can be used to offset this increase.

Figure 10 shows the results of changing the slew rate control settings to SR CLOCK = 5 and SR STEP = 2 while keeping the C1 capacitor value unchanged at 4.7 nF. In this way, the conversion time will be around 240 ms. The peak amplitude at the filter output can be further reduced by increasing the C1 value, or configuring a slower slew rate, or a combination of both.

Transient voltage protection

The AD5420 has built-in ESD protection diodes to prevent device damage under normal operating conditions. However, industrial control environments subject I/O circuits to much higher transients. To prevent excessive transient voltages from affecting the AD5420, external power diodes and inrush current limiting resistors may be required, as shown in Figure 1. The constraints on the resistor value (shown as 18 Ω in Figure 1) are that during normal operation, the output level of I _{OUT must remain within its voltage limit (AV DD} ), and the two protection diodes and resistor must Has the appropriate power rating. At 18 Ω, the voltage limit on the pin is reduced to V = I _MAX × R = 0.36 V for a 4 mA to 20 mA output. Further protection can be achieved through transient voltage suppressors (TVS) or transient absorbers. These components include unidirectional and bidirectional suppressors, available in a wide variety of isolation and breakdown voltage ratings. TVS should be calibrated with the lowest breakdown voltage as much as possible, and at the same time, it should not conduct within the range of normal current output. It is recommended to secure all remotely connected nodes.

In many process control applications, it is necessary to provide an isolation barrier between the controller and the controlled unit to protect and isolate the control circuitry from any dangerous common-mode voltages that may occur. Analog Devices' iCoupler family of products provides voltage isolation in excess of 2.5 kV. For more information about iCoupler products, please visit www.analog.com/icouplers . To reduce the number of isolators required, non-critical signals such as CLEAR can be connected to GND; FAULT and SDO can be left unconnected, thus only three signals need to be isolated. Note, however, that the FAULT or SDO pin is required to access the fault detection functionality of the AD5420.