This circuit utilizes a low-noise, low-dropout (LDO) linear regulator to power a wideband integrated PLL and VCO. Wideband voltage-controlled oscillators (VCOs) can be sensitive to power supply noise, so for best performance, an ultra-low-noise regulator is recommended.
The circuit shown in Figure 1 uses a fully integrated fractional-N PLL and VCO ADF4350 , which can generate frequencies in the range of 137.5 MHz to 4400 MHz. The ADF4350 uses an ultra-low noise 3.3 V The ADP150 regulator is powered for optimal LO phase noise performance.
The ADP150 LDO has a low integrated rms noise of only 9 μV (10 Hz to 100 kHz), helping to minimize VCO phase noise and reduce the effects of VCO pushing (equivalent to supply rejection).
Figure 2 is a photo of the evaluation board, which utilizes the ADP150 LDO to power the ADF4350. The ADP150 represents the industry's lowest noise, smallest package, and lowest cost LDO, available in a 4-pin, 0.8 mm x 0.8 mm, 0.4 mm pitch WLCSP package or a convenient 5-pin TSOT package. Therefore, adding the ADP150 to the design has minimal impact on system cost and board area, but can significantly improve phase noise performance.
The ADF4350 is a wideband PLL and VCO that includes three independent multi-band VCOs. Each VCO covers approximately 700 MHz (with some overlap between VCOs) with the lower frequencies generated by the output divider.
VCO push is measured by applying a stable DC tuning voltage to the ADF4350 VTUNE pin, then changing the supply voltage and measuring the frequency change. The pushing coefficient (P) is equal to the frequency change divided by the voltage change, as shown in Table 1.
VCO frequency (MHz) | V Tune (V) | VCO push(MHz/V) |
2200 | 2.5 | 0.73 |
3300 | 2.5 |
1.79 |
4400 | 2.5 |
5.99 |
In a PLL system, if the VCO push voltage is high, it means that the power supply noise will reduce the phase noise performance of the VCO; if the VCO push voltage is low, the power supply noise will not significantly reduce the phase noise performance. However, for high VCO push, a noisy power supply will have a greater impact on phase noise performance.
Experiments have shown that pushing reaches a maximum at the VCO output frequency of 4.4 GHz, so we compared VCO performance using different regulators at this frequency. The ADF4350 version A evaluation board uses the ADP3334 LDO regulator. The integrated rms noise of this regulator is 27 μV (integrated from 10 Hz to 100 kHz). In comparison, the ADP150 used in EVAL-ADF4350EB1Z version B only has 9 μV. To measure the impact of power supply noise, a more in-depth look at the VCO phase noise was performed using a narrow PLL loop bandwidth (10 kHz). Figure 3 is a schematic diagram of this setup.
For a more detailed analysis of output noise density versus frequency, please refer to the ADP3334 and ADP150 data sheets.
Figure 4 shows that the noise spectral density of the ADP3334 regulator is 25 nV/√Hz at 100 kHz offset. The ADP150 is 100 nV/√Hz (Figure 5).
The calculation formula for phase noise performance degradation caused by power supply noise is as follows:
Among them, L (LDO) is the noise contribution of the regulator to the VCO phase noise at the frequency offset fm (dBc/Hz); P is the VCO pushing coefficient (Hz/V); Sfm is the noise at a given frequency offset Spectral density (V/√Hz); fm is the frequency offset (Hz) corresponding to the measured noise spectral density.
The supply's noise contribution is then summed RSS-wise with the VCO's noise contribution (which itself is measured using a very low-noise power supply) to give the total noise at the VCO's output with a given regulator.
These noises are summed in RSS terms to give the desired VCO phase noise:
In this example, a noise spectral density offset of 100 kHz is selected and a push factor of 6 MHz/V is used, resulting in a VCO noise value of −110 dBc/Hz with an ideal power supply.
|
ADP3334 | ADP150 |
Regulator noise contribution (nV/√Hz) |
150 | 25 |
Regulator noise contribution (dBc/Hz) |
-104 | -119.5 |
Total calculated noise at VCO output (dBc/Hz) |
-103 | -109.5 |
VCO noise measurements at 100 kHz offset (dBc/Hz) |
-102.6 | -108.5 |
Integrated phase noise also improved from 1.95°rms to 1.4°rms. The measured results correlate very well with the calculated results and clearly demonstrate the benefits of using the ADP150 with the ADF4350.
For the complete design support package for this circuit note, please visit http://www.analog.com/CN0147-DesignSupport .
Blockdiagram
Devices | Class | introduce | Datasheet |
---|---|---|---|
ADF4350 | semiconductor;Analog mixed-signal IC | PLL FREQUENCY SYNTHESIZER, 250 MHz, QCC32 | Download |
ADP150 | semiconductor;Power management | 2.8 V FIXED POSITIVE LDO REGULATOR, 0.16 V DROPOUT, PBGA4 | Download |
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